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wdenkfe8c2802002-11-03 00:38:21 +00001/*
2 * (C) Copyright 2000
3 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
4 *
5 * (C) Copyright 2000
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * (C) Copyright 2001
10 * Advent Networks, Inc. <http://www.adventnetworks.com>
11 * Jay Monkman <jtm@smoothsmoothie.com>
12 *
Paul Gortmakerb30d41c2011-09-17 13:47:47 +000013 * Configuration settings for the SACSng 8260 board.
wdenkfe8c2802002-11-03 00:38:21 +000014 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020015 * SPDX-License-Identifier: GPL-2.0+
wdenkfe8c2802002-11-03 00:38:21 +000016 */
17
18#ifndef __CONFIG_H
19#define __CONFIG_H
20
Wolfgang Denk2ae18242010-10-06 09:05:45 +020021#define CONFIG_SYS_TEXT_BASE 0x40000000
22
wdenkfe8c2802002-11-03 00:38:21 +000023#undef DEBUG_BOOTP_EXT /* Debug received vendor fields */
24
wdenk78137c32003-09-15 18:00:00 +000025#undef CONFIG_LOGBUFFER /* External logbuffer support */
26
wdenkfe8c2802002-11-03 00:38:21 +000027/*****************************************************************************
28 *
29 * These settings must match the way _your_ board is set up
30 *
31 *****************************************************************************/
32
33/* What is the oscillator's (UX2) frequency in Hz? */
34#define CONFIG_8260_CLKIN 66666600
35
36/*-----------------------------------------------------------------------
37 * MODCK_H & MODCLK[1-3] - Ref: Section 9.2 in MPC8206 User Manual
38 *-----------------------------------------------------------------------
39 * What should MODCK_H be? It is dependent on the oscillator
40 * frequency, MODCK[1-3], and desired CPM and core frequencies.
41 * Here are some example values (all frequencies are in MHz):
42 *
43 * MODCK_H MODCK[1-3] Osc CPM Core S2-6 S2-7 S2-8
44 * ------- ---------- --- --- ---- ----- ----- -----
45 * 0x1 0x5 33 100 133 Open Close Open
46 * 0x1 0x6 33 100 166 Open Open Close
47 * 0x1 0x7 33 100 200 Open Open Open
48 *
49 * 0x2 0x2 33 133 133 Close Open Close
50 * 0x2 0x3 33 133 166 Close Open Open
51 * 0x2 0x4 33 133 200 Open Close Close
52 * 0x2 0x5 33 133 233 Open Close Open
53 * 0x2 0x6 33 133 266 Open Open Close
54 *
55 * 0x5 0x5 66 133 133 Open Close Open
56 * 0x5 0x6 66 133 166 Open Open Close
57 * 0x5 0x7 66 133 200 Open Open Open
58 * 0x6 0x0 66 133 233 Close Close Close
59 * 0x6 0x1 66 133 266 Close Close Open
60 * 0x6 0x2 66 133 300 Close Open Close
61 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020062#define CONFIG_SYS_SBC_MODCK_H 0x05
wdenkfe8c2802002-11-03 00:38:21 +000063
64/* Define this if you want to boot from 0x00000100. If you don't define
65 * this, you will need to program the bootloader to 0xfff00000, and
66 * get the hardware reset config words at 0xfe000000. The simplest
67 * way to do that is to program the bootloader at both addresses.
68 * It is suggested that you just let U-Boot live at 0x00000000.
69 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070#define CONFIG_SYS_SBC_BOOT_LOW 1
wdenkfe8c2802002-11-03 00:38:21 +000071
72/* What should the base address of the main FLASH be and how big is
Wolfgang Denk14d0a022010-10-07 21:51:12 +020073 * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/sacsng/config.mk
wdenkfe8c2802002-11-03 00:38:21 +000074 * The main FLASH is whichever is connected to *CS0.
75 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#define CONFIG_SYS_FLASH0_BASE 0x40000000
77#define CONFIG_SYS_FLASH0_SIZE 2
wdenkfe8c2802002-11-03 00:38:21 +000078
79/* What should the base address of the secondary FLASH be and how big
80 * is it (in Mbytes)? The secondary FLASH is whichever is connected
81 * to *CS6.
82 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083#define CONFIG_SYS_FLASH1_BASE 0x60000000
84#define CONFIG_SYS_FLASH1_SIZE 2
wdenkfe8c2802002-11-03 00:38:21 +000085
86/* Define CONFIG_VERY_BIG_RAM to allow use of SDRAMs larger than 256MBytes
87 */
88#define CONFIG_VERY_BIG_RAM 1
89
90/* What should be the base address of SDRAM DIMM and how big is
91 * it (in Mbytes)? This will normally auto-configure via the SPD.
92*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#define CONFIG_SYS_SDRAM0_BASE 0x00000000
94#define CONFIG_SYS_SDRAM0_SIZE 64
wdenkfe8c2802002-11-03 00:38:21 +000095
96/*
97 * Memory map example with 64 MB DIMM:
98 *
99 * 0x0000 0000 Exception Vector code, 8k
100 * :
101 * 0x0000 1FFF
102 * 0x0000 2000 Free for Application Use
103 * :
104 * :
105 *
106 * :
107 * :
108 * 0x03F5 FF30 Monitor Stack (Growing downward)
109 * Monitor Stack Buffer (0x80)
110 * 0x03F5 FFB0 Board Info Data
111 * 0x03F6 0000 Malloc Arena
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200112 * : CONFIG_ENV_SECT_SIZE, 16k
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113 * : CONFIG_SYS_MALLOC_LEN, 128k
wdenkfe8c2802002-11-03 00:38:21 +0000114 * 0x03FC 0000 RAM Copy of Monitor Code
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115 * : CONFIG_SYS_MONITOR_LEN, 256k
116 * 0x03FF FFFF [End of RAM], CONFIG_SYS_SDRAM_SIZE - 1
wdenkfe8c2802002-11-03 00:38:21 +0000117 */
118
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
120 CONFIG_SYS_POST_CPU)
wdenkfe8c2802002-11-03 00:38:21 +0000121
122
123/*
124 * select serial console configuration
125 *
126 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
127 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
128 * for SCC).
129 *
130 * if CONFIG_CONS_NONE is defined, then the serial console routines must
131 * defined elsewhere.
132 */
133#define CONFIG_CONS_ON_SMC 1 /* define if console on SMC */
134#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
135#undef CONFIG_CONS_NONE /* define if console on neither */
136#define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
137
138/*
139 * select ethernet configuration
140 *
141 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
142 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
143 * for FCC)
144 *
145 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -0500146 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenkfe8c2802002-11-03 00:38:21 +0000147 */
148
149#undef CONFIG_ETHER_ON_SCC
150#define CONFIG_ETHER_ON_FCC
151#undef CONFIG_ETHER_NONE /* define if ethernet on neither */
152
153#ifdef CONFIG_ETHER_ON_SCC
154#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
155#endif /* CONFIG_ETHER_ON_SCC */
156
157#ifdef CONFIG_ETHER_ON_FCC
158#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
wdenk78137c32003-09-15 18:00:00 +0000159#undef CONFIG_ETHER_LOOPBACK_TEST /* Ethernet external loopback test */
wdenkfe8c2802002-11-03 00:38:21 +0000160#define CONFIG_MII /* MII PHY management */
161#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
162/*
163 * Port pins used for bit-banged MII communictions (if applicable).
164 */
165
166#define MDIO_PORT 2 /* Port A=0, B=1, C=2, D=3 */
Luigi 'Comio' Mantellinibe225442009-10-10 12:42:22 +0200167#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
168 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
169#define MDC_DECLARE MDIO_DECLARE
170
wdenkfe8c2802002-11-03 00:38:21 +0000171#define MDIO_ACTIVE (iop->pdir |= 0x40000000)
172#define MDIO_TRISTATE (iop->pdir &= ~0x40000000)
173#define MDIO_READ ((iop->pdat & 0x40000000) != 0)
174
175#define MDIO(bit) if(bit) iop->pdat |= 0x40000000; \
176 else iop->pdat &= ~0x40000000
177
178#define MDC(bit) if(bit) iop->pdat |= 0x80000000; \
179 else iop->pdat &= ~0x80000000
180
181#define MIIDELAY udelay(50)
182#endif /* CONFIG_ETHER_ON_FCC */
183
184#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
185
186/*
187 * - RX clk is CLK11
188 * - TX clk is CLK12
189 */
Mike Frysingerd4590da2011-10-17 05:38:58 +0000190# define CONFIG_SYS_CMXSCR_VALUE1 (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
wdenkfe8c2802002-11-03 00:38:21 +0000191
192#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
193
194/*
195 * - Rx-CLK is CLK13
196 * - Tx-CLK is CLK14
197 * - Select bus for bd/buffers (see 28-13)
198 * - Enable Full Duplex in FSMR
199 */
Mike Frysingerd4590da2011-10-17 05:38:58 +0000200# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
201# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202# define CONFIG_SYS_CPMFCR_RAMTYPE 0
203# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
wdenkfe8c2802002-11-03 00:38:21 +0000204
205#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
206
207#define CONFIG_SHOW_BOOT_PROGRESS 1 /* boot progress enabled */
208
209/*
210 * Configure for RAM tests.
211 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#undef CONFIG_SYS_DRAM_TEST /* calls other tests in board.c */
wdenkfe8c2802002-11-03 00:38:21 +0000213
214
215/*
216 * Status LED for power up status feedback.
217 */
218#define CONFIG_STATUS_LED 1 /* Status LED enabled */
219
220#define STATUS_LED_PAR im_ioport.iop_ppara
221#define STATUS_LED_DIR im_ioport.iop_pdira
222#define STATUS_LED_ODR im_ioport.iop_podra
223#define STATUS_LED_DAT im_ioport.iop_pdata
224
225#define STATUS_LED_BIT 0x00000800 /* LED 0 is on PA.20 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define STATUS_LED_PERIOD (CONFIG_SYS_HZ)
wdenkfe8c2802002-11-03 00:38:21 +0000227#define STATUS_LED_STATE STATUS_LED_OFF
228#define STATUS_LED_BIT1 0x00001000 /* LED 1 is on PA.19 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ)
wdenkfe8c2802002-11-03 00:38:21 +0000230#define STATUS_LED_STATE1 STATUS_LED_OFF
231#define STATUS_LED_BIT2 0x00002000 /* LED 2 is on PA.18 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ/2)
wdenkfe8c2802002-11-03 00:38:21 +0000233#define STATUS_LED_STATE2 STATUS_LED_ON
234
235#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
236
237#define STATUS_LED_YELLOW 0
238#define STATUS_LED_GREEN 1
239#define STATUS_LED_RED 2
240#define STATUS_LED_BOOT 1
241
242
243/*
wdenk1d0350e2002-11-11 21:14:20 +0000244 * Select SPI support configuration
wdenkfe8c2802002-11-03 00:38:21 +0000245 */
wdenk1d0350e2002-11-11 21:14:20 +0000246#define CONFIG_SOFT_SPI /* Enable SPI driver */
247#define MAX_SPI_BYTES 4 /* Maximum number of bytes we can handle */
wdenk8bde7f72003-06-27 21:31:46 +0000248#undef DEBUG_SPI /* Disable SPI debugging */
249
wdenkfe8c2802002-11-03 00:38:21 +0000250/*
251 * Software (bit-bang) SPI driver configuration
252 */
253#ifdef CONFIG_SOFT_SPI
254
255/*
256 * Software (bit-bang) SPI driver configuration
257 */
258#define I2C_SCLK 0x00002000 /* PD 18: Shift clock */
259#define I2C_MOSI 0x00004000 /* PD 17: Master Out, Slave In */
260#define I2C_MISO 0x00008000 /* PD 16: Master In, Slave Out */
261
262#undef SPI_INIT /* no port initialization needed */
263#define SPI_READ ((immr->im_ioport.iop_pdatd & I2C_MISO) != 0)
Wolfgang Denkced209c2008-07-03 22:39:21 +0200264#define SPI_SDA(bit) do { \
265 if(bit) immr->im_ioport.iop_pdatd |= I2C_MOSI; \
266 else immr->im_ioport.iop_pdatd &= ~I2C_MOSI; \
267 } while (0)
268#define SPI_SCL(bit) do { \
269 if(bit) immr->im_ioport.iop_pdatd |= I2C_SCLK; \
270 else immr->im_ioport.iop_pdatd &= ~I2C_SCLK; \
271 } while (0)
wdenk1d0350e2002-11-11 21:14:20 +0000272#define SPI_DELAY /* No delay is needed */
wdenkfe8c2802002-11-03 00:38:21 +0000273#endif /* CONFIG_SOFT_SPI */
274
275
276/*
277 * select I2C support configuration
278 *
279 * Supported configurations are {none, software, hardware} drivers.
280 * If the software driver is chosen, there are some additional
281 * configuration items that the driver uses to drive the port pins.
282 */
Heiko Schocherea818db2013-01-29 08:53:15 +0100283#define CONFIG_SYS_I2C
284#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
285#define CONFIG_SYS_I2C_SOFT_SPEED 400000
286#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
wdenkfe8c2802002-11-03 00:38:21 +0000287/*
288 * Software (bit-bang) I2C driver configuration
289 */
wdenkfe8c2802002-11-03 00:38:21 +0000290#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
291#define I2C_ACTIVE (iop->pdir |= 0x00010000)
292#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
293#define I2C_READ ((iop->pdat & 0x00010000) != 0)
294#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
295 else iop->pdat &= ~0x00010000
296#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
297 else iop->pdat &= ~0x00020000
298#define I2C_DELAY udelay(20) /* 1/4 I2C clock duration */
wdenkfe8c2802002-11-03 00:38:21 +0000299
300/* Define this to reserve an entire FLASH sector for
301 * environment variables. Otherwise, the environment will be
302 * put in the same sector as U-Boot, and changing variables
303 * will erase U-Boot temporarily
304 */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200305#define CONFIG_ENV_IN_OWN_SECT 1
wdenkfe8c2802002-11-03 00:38:21 +0000306
307/* Define this to contain any number of null terminated strings that
Robert P. J. Day1bce2ae2013-09-16 07:15:45 -0400308 * will be part of the default environment compiled into the boot image.
wdenkfe8c2802002-11-03 00:38:21 +0000309 */
310#define CONFIG_EXTRA_ENV_SETTINGS \
wdenk78137c32003-09-15 18:00:00 +0000311"quiet=0\0" \
312"serverip=192.168.123.205\0" \
wdenkfe8c2802002-11-03 00:38:21 +0000313"ipaddr=192.168.123.203\0" \
314"checkhostname=VR8500\0" \
315"reprog="\
wdenk78137c32003-09-15 18:00:00 +0000316 "bootp; " \
wdenkfe8c2802002-11-03 00:38:21 +0000317 "tftpboot 0x140000 /bdi2000/u-boot.bin; " \
318 "protect off 60000000 6003FFFF; " \
319 "erase 60000000 6003FFFF; " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100320 "cp.b 140000 60000000 ${filesize}; " \
wdenkfe8c2802002-11-03 00:38:21 +0000321 "protect on 60000000 6003FFFF\0" \
322"copyenv="\
323 "protect off 60040000 6004FFFF; " \
324 "erase 60040000 6004FFFF; " \
325 "cp.b 40040000 60040000 10000; " \
326 "protect on 60040000 6004FFFF\0" \
327"copyprog="\
328 "protect off 60000000 6003FFFF; " \
329 "erase 60000000 6003FFFF; " \
330 "cp.b 40000000 60000000 40000; " \
331 "protect on 60000000 6003FFFF\0" \
332"zapenv="\
333 "protect off 40040000 4004FFFF; " \
334 "erase 40040000 4004FFFF; " \
335 "protect on 40040000 4004FFFF\0" \
336"zapotherenv="\
337 "protect off 60040000 6004FFFF; " \
338 "erase 60040000 6004FFFF; " \
339 "protect on 60040000 6004FFFF\0" \
340"root-on-initrd="\
341 "setenv bootcmd "\
342 "version\\;" \
343 "echo\\;" \
344 "bootp\\;" \
345 "setenv bootargs root=/dev/ram0 rw quiet " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100346 "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
wdenkfe8c2802002-11-03 00:38:21 +0000347 "run boot-hook\\;" \
348 "bootm\0" \
349"root-on-initrd-debug="\
350 "setenv bootcmd "\
351 "version\\;" \
352 "echo\\;" \
353 "bootp\\;" \
354 "setenv bootargs root=/dev/ram0 rw debug " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100355 "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
wdenkfe8c2802002-11-03 00:38:21 +0000356 "run debug-hook\\;" \
357 "run boot-hook\\;" \
358 "bootm\0" \
359"root-on-nfs="\
360 "setenv bootcmd "\
361 "version\\;" \
362 "echo\\;" \
363 "bootp\\;" \
364 "setenv bootargs root=/dev/nfs rw quiet " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100365 "nfsroot=\\${serverip}:\\${rootpath} " \
366 "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
wdenkfe8c2802002-11-03 00:38:21 +0000367 "run boot-hook\\;" \
368 "bootm\0" \
369"root-on-nfs-debug="\
370 "setenv bootcmd "\
371 "version\\;" \
372 "echo\\;" \
373 "bootp\\;" \
374 "setenv bootargs root=/dev/nfs rw debug " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100375 "nfsroot=\\${serverip}:\\${rootpath} " \
376 "ip=\\${ipaddr}:\\${serverip}:\\${gatewayip}:\\${netmask}:\\${hostname}::off\\;" \
wdenkfe8c2802002-11-03 00:38:21 +0000377 "run debug-hook\\;" \
378 "run boot-hook\\;" \
379 "bootm\0" \
380"debug-checkout="\
381 "setenv checkhostname;" \
382 "setenv ethaddr 00:09:70:00:00:01;" \
383 "bootp;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100384 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} debug " \
385 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenkfe8c2802002-11-03 00:38:21 +0000386 "run debug-hook;" \
387 "run boot-hook;" \
388 "bootm\0" \
389"debug-hook="\
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100390 "echo ipaddr ${ipaddr};" \
391 "echo serverip ${serverip};" \
392 "echo gatewayip ${gatewayip};" \
393 "echo netmask ${netmask};" \
394 "echo hostname ${hostname}\0" \
wdenkfe8c2802002-11-03 00:38:21 +0000395"ana=run adc ; run dac\0" \
396"adc=run adc-12 ; run adc-34\0" \
Peter Tyser0f89c542009-04-18 22:34:03 -0500397"adc-12=echo ### ADC-12 ; i2c md e 81 e\0" \
398"adc-34=echo ### ADC-34 ; i2c md f 81 e\0" \
399"dac=echo ### DAC ; i2c md 11 81 5\0" \
wdenk78137c32003-09-15 18:00:00 +0000400"boot-hook=echo\0"
wdenkfe8c2802002-11-03 00:38:21 +0000401
402/* What should the console's baud rate be? */
403#define CONFIG_BAUDRATE 9600
404
405/* Ethernet MAC address */
406#define CONFIG_ETHADDR 00:09:70:00:00:00
407
408/* The default Ethernet MAC address can be overwritten just once */
409#ifdef CONFIG_ETHADDR
410#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
411#endif
412
413/*
414 * Define this to do some miscellaneous board-specific initialization.
415 */
416#define CONFIG_MISC_INIT_R
417
418/* Set to a positive value to delay for running BOOTCOMMAND */
419#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
420
421/* Be selective on what keys can delay or stop the autoboot process
422 * To stop use: " "
423 */
424#define CONFIG_AUTOBOOT_KEYED
Stefan Roesef2302d42008-08-06 14:05:38 +0200425#define CONFIG_AUTOBOOT_PROMPT "Autobooting...\n"
wdenkfe8c2802002-11-03 00:38:21 +0000426#define CONFIG_AUTOBOOT_STOP_STR " "
427#undef CONFIG_AUTOBOOT_DELAY_STR
428#define CONFIG_ZERO_BOOTDELAY_CHECK
429#define DEBUG_BOOTKEYS 0
430
431/* Define a command string that is automatically executed when no character
432 * is read on the console interface withing "Boot Delay" after reset.
433 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200434#undef CONFIG_BOOT_ROOT_INITRD /* Use ram disk for the root file system */
wdenkb79a11c2004-03-25 15:14:43 +0000435#define CONFIG_BOOT_ROOT_NFS /* Use a NFS mounted root file system */
wdenkfe8c2802002-11-03 00:38:21 +0000436
wdenk42dfe7a2004-03-14 22:25:36 +0000437#ifdef CONFIG_BOOT_ROOT_INITRD
wdenkfe8c2802002-11-03 00:38:21 +0000438#define CONFIG_BOOTCOMMAND \
439 "version;" \
440 "echo;" \
441 "bootp;" \
442 "setenv bootargs root=/dev/ram0 rw quiet " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100443 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenkfe8c2802002-11-03 00:38:21 +0000444 "run boot-hook;" \
445 "bootm"
446#endif /* CONFIG_BOOT_ROOT_INITRD */
447
wdenk42dfe7a2004-03-14 22:25:36 +0000448#ifdef CONFIG_BOOT_ROOT_NFS
wdenkfe8c2802002-11-03 00:38:21 +0000449#define CONFIG_BOOTCOMMAND \
450 "version;" \
451 "echo;" \
452 "bootp;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100453 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} quiet " \
454 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenkfe8c2802002-11-03 00:38:21 +0000455 "run boot-hook;" \
456 "bootm"
457#endif /* CONFIG_BOOT_ROOT_NFS */
458
459#define CONFIG_BOOTP_RANDOM_DELAY /* Randomize the BOOTP retry delay */
Przemyslaw Marczak3c1c68c2014-03-25 10:58:19 +0100460#define CONFIG_LIB_RAND
wdenkfe8c2802002-11-03 00:38:21 +0000461
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -0500462/*
463 * BOOTP options
wdenkfe8c2802002-11-03 00:38:21 +0000464 */
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -0500465#define CONFIG_BOOTP_SUBNETMASK
466#define CONFIG_BOOTP_GATEWAY
467#define CONFIG_BOOTP_HOSTNAME
468#define CONFIG_BOOTP_BOOTPATH
469#define CONFIG_BOOTP_BOOTFILESIZE
470#define CONFIG_BOOTP_DNS
471#define CONFIG_BOOTP_DNS2
472#define CONFIG_BOOTP_SEND_HOSTNAME
473
wdenkfe8c2802002-11-03 00:38:21 +0000474
475/* undef this to save memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200476#define CONFIG_SYS_LONGHELP
wdenkfe8c2802002-11-03 00:38:21 +0000477
478/* Monitor Command Prompt */
wdenkfe8c2802002-11-03 00:38:21 +0000479
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200480#undef CONFIG_SYS_HUSH_PARSER
481#ifdef CONFIG_SYS_HUSH_PARSER
wdenkfe8c2802002-11-03 00:38:21 +0000482#endif
483
wdenk1d0350e2002-11-11 21:14:20 +0000484/* When CONFIG_TIMESTAMP is selected, the timestamp (date and time)
485 * of an image is printed by image commands like bootm or iminfo.
486 */
487#define CONFIG_TIMESTAMP
488
wdenk42d1f032003-10-15 23:53:47 +0000489/* If this variable is defined, an environment variable named "ver"
wdenk78137c32003-09-15 18:00:00 +0000490 * is created by U-Boot showing the U-Boot version.
491 */
492#define CONFIG_VERSION_VARIABLE
493
Jon Loeliger46da1e92007-07-04 22:33:30 -0500494
495/*
496 * Command line configuration.
497 */
498#include <config_cmd_default.h>
499
500#define CONFIG_CMD_ELF
501#define CONFIG_CMD_ASKENV
502#define CONFIG_CMD_I2C
503#define CONFIG_CMD_SPI
504#define CONFIG_CMD_SDRAM
505#define CONFIG_CMD_REGINFO
506#define CONFIG_CMD_IMMAP
507#define CONFIG_CMD_IRQ
508#define CONFIG_CMD_PING
509
510#undef CONFIG_CMD_KGDB
511
wdenkfe8c2802002-11-03 00:38:21 +0000512#ifdef CONFIG_ETHER_ON_FCC
Jon Loeliger46da1e92007-07-04 22:33:30 -0500513#define CONFIG_CMD_MII
514#endif
515
wdenkfe8c2802002-11-03 00:38:21 +0000516
517/* Where do the internal registers live? */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200518#define CONFIG_SYS_IMMR 0xF0000000
wdenkfe8c2802002-11-03 00:38:21 +0000519
wdenk78137c32003-09-15 18:00:00 +0000520#undef CONFIG_WATCHDOG /* disable the watchdog */
521
wdenkfe8c2802002-11-03 00:38:21 +0000522/*****************************************************************************
523 *
524 * You should not have to modify any of the following settings
525 *
526 *****************************************************************************/
527
wdenkfe8c2802002-11-03 00:38:21 +0000528#define CONFIG_SACSng 1 /* munged for the SACSng */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500529#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenkfe8c2802002-11-03 00:38:21 +0000530
wdenkfe8c2802002-11-03 00:38:21 +0000531/*
532 * Miscellaneous configurable options
533 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200534#define CONFIG_SYS_BOOTM_HEADER_QUIET 1 /* Suppress the image header dump */
wdenk42d1f032003-10-15 23:53:47 +0000535 /* in the bootm command. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200536#define CONFIG_SYS_BOOTM_PROGESS_QUIET 1 /* Suppress the progress displays, */
wdenk42d1f032003-10-15 23:53:47 +0000537 /* "## <message>" from the bootm cmd */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200538#define CONFIG_SYS_BOOTP_CHECK_HOSTNAME 1 /* If checkhostname environment is */
wdenk42d1f032003-10-15 23:53:47 +0000539 /* defined, then the hostname param */
540 /* validated against checkhostname. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200541#define CONFIG_SYS_BOOTP_RETRY_COUNT 0x40000000 /* # of timeouts before giving up */
542#define CONFIG_SYS_BOOTP_SHORT_RANDOM_DELAY 1 /* Use a short random delay value */
wdenk42d1f032003-10-15 23:53:47 +0000543 /* (limited to maximum of 1024 msec) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200544#define CONFIG_SYS_CHK_FOR_ABORT_AT_LEAST_ONCE 1
wdenk42d1f032003-10-15 23:53:47 +0000545 /* Check for abort key presses */
546 /* at least once in dependent of the */
547 /* CONFIG_BOOTDELAY value. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200548#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Don't print console @ startup */
549#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1 /* Echo the inverted Ethernet link */
wdenk42d1f032003-10-15 23:53:47 +0000550 /* state to the fault LED. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200551#define CONFIG_SYS_FAULT_MII_ADDR 0x02 /* MII addr of the PHY to check for */
wdenk42d1f032003-10-15 23:53:47 +0000552 /* the Ethernet link state. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200553#define CONFIG_SYS_STATUS_FLASH_UNTIL_TFTP_OK 1 /* Keeping the status LED flashing */
wdenk42d1f032003-10-15 23:53:47 +0000554 /* until the TFTP is successful. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200555#define CONFIG_SYS_STATUS_OFF_AFTER_NETBOOT 1 /* After a successful netboot, */
wdenk42d1f032003-10-15 23:53:47 +0000556 /* turn off the STATUS LEDs. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200557#define CONFIG_SYS_TFTP_BLINK_STATUS_ON_DATA_IN 1 /* Blink status LED based on */
wdenk42d1f032003-10-15 23:53:47 +0000558 /* incoming data. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200559#define CONFIG_SYS_TFTP_BLOCKS_PER_HASH 100 /* For every XX blocks, output a '#' */
wdenk42d1f032003-10-15 23:53:47 +0000560 /* to signify that tftp is moving. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200561#define CONFIG_SYS_TFTP_HASHES_PER_FLASH 200 /* For every '#' hashes, */
wdenk42d1f032003-10-15 23:53:47 +0000562 /* flash the status LED. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200563#define CONFIG_SYS_TFTP_HASHES_PER_LINE 65 /* Only output XX '#'s per line */
wdenk42d1f032003-10-15 23:53:47 +0000564 /* during the tftp file transfer. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200565#define CONFIG_SYS_TFTP_PROGESS_QUIET 1 /* Suppress the progress displays */
wdenk42d1f032003-10-15 23:53:47 +0000566 /* '#'s from the tftp command. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200567#define CONFIG_SYS_TFTP_STATUS_QUIET 1 /* Suppress the status displays */
wdenk42d1f032003-10-15 23:53:47 +0000568 /* issued during the tftp command. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200569#define CONFIG_SYS_TFTP_TIMEOUT_COUNT 5 /* How many timeouts TFTP will allow */
wdenk78137c32003-09-15 18:00:00 +0000570 /* before it gives up. */
571
Jon Loeliger46da1e92007-07-04 22:33:30 -0500572#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200573# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkfe8c2802002-11-03 00:38:21 +0000574#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200575# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkfe8c2802002-11-03 00:38:21 +0000576#endif
577
578/* Print Buffer Size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200579#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16)
wdenkfe8c2802002-11-03 00:38:21 +0000580
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200581#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
wdenkfe8c2802002-11-03 00:38:21 +0000582
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200583#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkfe8c2802002-11-03 00:38:21 +0000584
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200585#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
wdenkfe8c2802002-11-03 00:38:21 +0000586
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200587#define CONFIG_SYS_ALT_MEMTEST /* Select full-featured memory test */
588#define CONFIG_SYS_MEMTEST_START 0x2000 /* memtest works from the end of */
wdenkfe8c2802002-11-03 00:38:21 +0000589 /* the exception vector table */
590 /* to the end of the DRAM */
591 /* less monitor and malloc area */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200592#define CONFIG_SYS_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
593#define CONFIG_SYS_MEM_END_USAGE ( CONFIG_SYS_MONITOR_LEN \
594 + CONFIG_SYS_MALLOC_LEN \
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200595 + CONFIG_ENV_SECT_SIZE \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200596 + CONFIG_SYS_STACK_USAGE )
wdenkfe8c2802002-11-03 00:38:21 +0000597
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200598#define CONFIG_SYS_MEMTEST_END ( CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 \
599 - CONFIG_SYS_MEM_END_USAGE )
wdenkfe8c2802002-11-03 00:38:21 +0000600
wdenkfe8c2802002-11-03 00:38:21 +0000601/*
602 * Low Level Configuration Settings
603 * (address mappings, register initial values, etc.)
604 * You should know what you are doing if you make changes here.
605 */
606
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200607#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
608#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
609#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM0_BASE
610#define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM0_SIZE
wdenkfe8c2802002-11-03 00:38:21 +0000611
612/*-----------------------------------------------------------------------
613 * Hard Reset Configuration Words
614 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200615#if defined(CONFIG_SYS_SBC_BOOT_LOW)
616# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
wdenkfe8c2802002-11-03 00:38:21 +0000617#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200618# define CONFIG_SYS_SBC_HRCW_BOOT_FLAGS (0)
619#endif /* defined(CONFIG_SYS_SBC_BOOT_LOW) */
wdenkfe8c2802002-11-03 00:38:21 +0000620
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200621/* get the HRCW ISB field from CONFIG_SYS_IMMR */
622#define CONFIG_SYS_SBC_HRCW_IMMR ( ((CONFIG_SYS_IMMR & 0x10000000) >> 10) | \
623 ((CONFIG_SYS_IMMR & 0x01000000) >> 7) | \
624 ((CONFIG_SYS_IMMR & 0x00100000) >> 4) )
wdenkfe8c2802002-11-03 00:38:21 +0000625
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200626#define CONFIG_SYS_HRCW_MASTER ( HRCW_BPS10 | \
wdenkfe8c2802002-11-03 00:38:21 +0000627 HRCW_DPPC11 | \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200628 CONFIG_SYS_SBC_HRCW_IMMR | \
wdenkfe8c2802002-11-03 00:38:21 +0000629 HRCW_MMR00 | \
630 HRCW_LBPC11 | \
631 HRCW_APPC10 | \
632 HRCW_CS10PC00 | \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200633 (CONFIG_SYS_SBC_MODCK_H & HRCW_MODCK_H1111) | \
634 CONFIG_SYS_SBC_HRCW_BOOT_FLAGS )
wdenkfe8c2802002-11-03 00:38:21 +0000635
636/* no slaves */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200637#define CONFIG_SYS_HRCW_SLAVE1 0
638#define CONFIG_SYS_HRCW_SLAVE2 0
639#define CONFIG_SYS_HRCW_SLAVE3 0
640#define CONFIG_SYS_HRCW_SLAVE4 0
641#define CONFIG_SYS_HRCW_SLAVE5 0
642#define CONFIG_SYS_HRCW_SLAVE6 0
643#define CONFIG_SYS_HRCW_SLAVE7 0
wdenkfe8c2802002-11-03 00:38:21 +0000644
645/*-----------------------------------------------------------------------
646 * Definitions for initial stack pointer and data area (in DPRAM)
647 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200648#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200649#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200650#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200651#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkfe8c2802002-11-03 00:38:21 +0000652
653/*-----------------------------------------------------------------------
654 * Start addresses for the final memory configuration
655 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200656 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
657 * Note also that the logic that sets CONFIG_SYS_RAMBOOT is platform dependent.
wdenkfe8c2802002-11-03 00:38:21 +0000658 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200659#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH0_BASE
wdenkfe8c2802002-11-03 00:38:21 +0000660
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200661#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
662# define CONFIG_SYS_RAMBOOT
wdenkfe8c2802002-11-03 00:38:21 +0000663#endif
664
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200665#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
666#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkfe8c2802002-11-03 00:38:21 +0000667
668/*
669 * For booting Linux, the board info and command line data
670 * have to be in the first 8 MB of memory, since this is
671 * the maximum mapped by the Linux kernel during initialization.
672 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200673#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkfe8c2802002-11-03 00:38:21 +0000674
675/*-----------------------------------------------------------------------
676 * FLASH and environment organization
677 */
678
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200679#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
680#undef CONFIG_SYS_FLASH_PROTECTION /* use hardware protection */
681#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
682#define CONFIG_SYS_MAX_FLASH_SECT (64+4) /* max number of sectors on one chip */
wdenkfe8c2802002-11-03 00:38:21 +0000683
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200684#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
685#define CONFIG_SYS_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
wdenkfe8c2802002-11-03 00:38:21 +0000686
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200687#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200688# define CONFIG_ENV_IS_IN_FLASH 1
wdenkfe8c2802002-11-03 00:38:21 +0000689
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200690# ifdef CONFIG_ENV_IN_OWN_SECT
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200691# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200692# define CONFIG_ENV_SECT_SIZE 0x10000
wdenkfe8c2802002-11-03 00:38:21 +0000693# else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200694# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN - CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200695# define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
696# define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sect real size */
697# endif /* CONFIG_ENV_IN_OWN_SECT */
wdenkfe8c2802002-11-03 00:38:21 +0000698
699#else
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200700# define CONFIG_ENV_IS_IN_NVRAM 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200701# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200702# define CONFIG_ENV_SIZE 0x200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200703#endif /* CONFIG_SYS_RAMBOOT */
wdenkfe8c2802002-11-03 00:38:21 +0000704
705/*-----------------------------------------------------------------------
706 * Cache Configuration
707 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200708#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
wdenkfe8c2802002-11-03 00:38:21 +0000709
Jon Loeliger46da1e92007-07-04 22:33:30 -0500710#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200711# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenkfe8c2802002-11-03 00:38:21 +0000712#endif
713
714/*-----------------------------------------------------------------------
715 * HIDx - Hardware Implementation-dependent Registers 2-11
716 *-----------------------------------------------------------------------
717 * HID0 also contains cache control - initially enable both caches and
718 * invalidate contents, then the final state leaves only the instruction
719 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
720 * but Soft reset does not.
721 *
722 * HID1 has only read-only information - nothing to set.
723 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200724#define CONFIG_SYS_HID0_INIT (HID0_ICE |\
wdenkfe8c2802002-11-03 00:38:21 +0000725 HID0_DCE |\
726 HID0_ICFI |\
727 HID0_DCI |\
728 HID0_IFEM |\
729 HID0_ABE)
730
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200731#define CONFIG_SYS_HID0_FINAL (HID0_ICE |\
wdenkfe8c2802002-11-03 00:38:21 +0000732 HID0_IFEM |\
733 HID0_ABE |\
734 HID0_EMCP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200735#define CONFIG_SYS_HID2 0
wdenkfe8c2802002-11-03 00:38:21 +0000736
737/*-----------------------------------------------------------------------
738 * RMR - Reset Mode Register
739 *-----------------------------------------------------------------------
740 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200741#define CONFIG_SYS_RMR 0
wdenkfe8c2802002-11-03 00:38:21 +0000742
743/*-----------------------------------------------------------------------
744 * BCR - Bus Configuration 4-25
745 *-----------------------------------------------------------------------
746 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200747#define CONFIG_SYS_BCR (BCR_ETM)
wdenkfe8c2802002-11-03 00:38:21 +0000748
749/*-----------------------------------------------------------------------
750 * SIUMCR - SIU Module Configuration 4-31
751 *-----------------------------------------------------------------------
752 */
753
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200754#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC11 |\
wdenkfe8c2802002-11-03 00:38:21 +0000755 SIUMCR_L2CPC00 |\
756 SIUMCR_APPC10 |\
757 SIUMCR_MMR00)
758
759
760/*-----------------------------------------------------------------------
761 * SYPCR - System Protection Control 11-9
762 * SYPCR can only be written once after reset!
763 *-----------------------------------------------------------------------
764 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
765 */
wdenk78137c32003-09-15 18:00:00 +0000766#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200767#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\
wdenk78137c32003-09-15 18:00:00 +0000768 SYPCR_BMT |\
769 SYPCR_PBME |\
770 SYPCR_LBME |\
771 SYPCR_SWRI |\
772 SYPCR_SWP |\
wdenk42d1f032003-10-15 23:53:47 +0000773 SYPCR_SWE)
wdenk78137c32003-09-15 18:00:00 +0000774#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200775#define CONFIG_SYS_SYPCR (SYPCR_SWTC |\
wdenkfe8c2802002-11-03 00:38:21 +0000776 SYPCR_BMT |\
777 SYPCR_PBME |\
778 SYPCR_LBME |\
779 SYPCR_SWRI |\
780 SYPCR_SWP)
wdenk78137c32003-09-15 18:00:00 +0000781#endif /* CONFIG_WATCHDOG */
wdenkfe8c2802002-11-03 00:38:21 +0000782
783/*-----------------------------------------------------------------------
784 * TMCNTSC - Time Counter Status and Control 4-40
785 *-----------------------------------------------------------------------
786 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
787 * and enable Time Counter
788 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200789#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC |\
wdenkfe8c2802002-11-03 00:38:21 +0000790 TMCNTSC_ALR |\
791 TMCNTSC_TCF |\
792 TMCNTSC_TCE)
793
794/*-----------------------------------------------------------------------
795 * PISCR - Periodic Interrupt Status and Control 4-42
796 *-----------------------------------------------------------------------
797 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
798 * Periodic timer
799 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200800#define CONFIG_SYS_PISCR (PISCR_PS |\
wdenkfe8c2802002-11-03 00:38:21 +0000801 PISCR_PTF |\
802 PISCR_PTE)
803
804/*-----------------------------------------------------------------------
805 * SCCR - System Clock Control 9-8
806 *-----------------------------------------------------------------------
807 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200808#define CONFIG_SYS_SCCR 0
wdenkfe8c2802002-11-03 00:38:21 +0000809
810/*-----------------------------------------------------------------------
811 * RCCR - RISC Controller Configuration 13-7
812 *-----------------------------------------------------------------------
813 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200814#define CONFIG_SYS_RCCR 0
wdenkfe8c2802002-11-03 00:38:21 +0000815
816/*
817 * Initialize Memory Controller:
818 *
819 * Bank Bus Machine PortSz Device
820 * ---- --- ------- ------ ------
821 * 0 60x GPCM 16 bit FLASH (primary flash - 2MB)
822 * 1 60x GPCM -- bit (Unused)
823 * 2 60x SDRAM 64 bit SDRAM (DIMM)
824 * 3 60x SDRAM 64 bit SDRAM (DIMM)
825 * 4 60x GPCM -- bit (Unused)
826 * 5 60x GPCM -- bit (Unused)
827 * 6 60x GPCM 16 bit FLASH (secondary flash - 2MB)
828 */
829
830/*-----------------------------------------------------------------------
831 * BR0,BR1 - Base Register
832 * Ref: Section 10.3.1 on page 10-14
833 * OR0,OR1 - Option Register
834 * Ref: Section 10.3.2 on page 10-18
835 *-----------------------------------------------------------------------
836 */
837
838/* Bank 0 - Primary FLASH
839 */
840
841/* BR0 is configured as follows:
842 *
843 * - Base address of 0x40000000
844 * - 16 bit port size
845 * - Data errors checking is disabled
846 * - Read and write access
847 * - GPCM 60x bus
848 * - Access are handled by the memory controller according to MSEL
849 * - Not used for atomic operations
850 * - No data pipelining is done
851 * - Valid
852 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200853#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH0_BASE & BRx_BA_MSK) |\
wdenkfe8c2802002-11-03 00:38:21 +0000854 BRx_PS_16 |\
855 BRx_MS_GPCM_P |\
856 BRx_V)
857
858/* OR0 is configured as follows:
859 *
860 * - 4 MB
861 * - *BCTL0 is asserted upon access to the current memory bank
862 * - *CW / *WE are negated a quarter of a clock earlier
863 * - *CS is output at the same time as the address lines
864 * - Uses a clock cycle length of 5
865 * - *PSDVAL is generated internally by the memory controller
866 * unless *GTA is asserted earlier externally.
867 * - Relaxed timing is generated by the GPCM for accesses
868 * initiated to this memory region.
869 * - One idle clock is inserted between a read access from the
870 * current bank and the next access.
871 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200872#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH0_SIZE) |\
wdenkfe8c2802002-11-03 00:38:21 +0000873 ORxG_CSNT |\
874 ORxG_ACS_DIV1 |\
875 ORxG_SCY_5_CLK |\
876 ORxG_TRLX |\
877 ORxG_EHTR)
878
879/*-----------------------------------------------------------------------
880 * BR2,BR3 - Base Register
881 * Ref: Section 10.3.1 on page 10-14
882 * OR2,OR3 - Option Register
883 * Ref: Section 10.3.2 on page 10-16
884 *-----------------------------------------------------------------------
885 */
886
887/* Bank 2,3 - SDRAM DIMM
888 */
889
890/* The BR2 is configured as follows:
891 *
892 * - Base address of 0x00000000
893 * - 64 bit port size (60x bus only)
894 * - Data errors checking is disabled
895 * - Read and write access
896 * - SDRAM 60x bus
897 * - Access are handled by the memory controller according to MSEL
898 * - Not used for atomic operations
899 * - No data pipelining is done
900 * - Valid
901 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200902#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
wdenkfe8c2802002-11-03 00:38:21 +0000903 BRx_PS_64 |\
904 BRx_MS_SDRAM_P |\
905 BRx_V)
906
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200907#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_SDRAM0_BASE & BRx_BA_MSK) |\
wdenkfe8c2802002-11-03 00:38:21 +0000908 BRx_PS_64 |\
909 BRx_MS_SDRAM_P |\
910 BRx_V)
911
912/* With a 64 MB DIMM, the OR2 is configured as follows:
913 *
914 * - 64 MB
915 * - 4 internal banks per device
916 * - Row start address bit is A8 with PSDMR[PBI] = 0
917 * - 12 row address lines
918 * - Back-to-back page mode
919 * - Internal bank interleaving within save device enabled
920 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200921#if (CONFIG_SYS_SDRAM0_SIZE == 64)
922#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_SDRAM0_SIZE) |\
wdenkfe8c2802002-11-03 00:38:21 +0000923 ORxS_BPD_4 |\
924 ORxS_ROWST_PBI0_A8 |\
925 ORxS_NUMR_12)
926#else
927#error "INVALID SDRAM CONFIGURATION"
928#endif
929
930/*-----------------------------------------------------------------------
931 * PSDMR - 60x Bus SDRAM Mode Register
932 * Ref: Section 10.3.3 on page 10-21
933 *-----------------------------------------------------------------------
934 */
935
936/* Address that the DIMM SPD memory lives at.
937 */
938#define SDRAM_SPD_ADDR 0x50
939
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200940#if (CONFIG_SYS_SDRAM0_SIZE == 64)
wdenkfe8c2802002-11-03 00:38:21 +0000941/* With a 64 MB DIMM, the PSDMR is configured as follows:
942 *
943 * - Bank Based Interleaving,
944 * - Refresh Enable,
945 * - Address Multiplexing where A5 is output on A14 pin
946 * (A6 on A15, and so on),
947 * - use address pins A14-A16 as bank select,
948 * - A9 is output on SDA10 during an ACTIVATE command,
949 * - earliest timing for ACTIVATE command after REFRESH command is 7 clocks,
950 * - earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
951 * is 3 clocks,
952 * - earliest timing for READ/WRITE command after ACTIVATE command is
953 * 2 clocks,
954 * - earliest timing for PRECHARGE after last data was read is 1 clock,
955 * - earliest timing for PRECHARGE after last data was written is 1 clock,
956 * - CAS Latency is 2.
957 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200958#define CONFIG_SYS_PSDMR (PSDMR_RFEN |\
wdenkfe8c2802002-11-03 00:38:21 +0000959 PSDMR_SDAM_A14_IS_A5 |\
960 PSDMR_BSMA_A14_A16 |\
961 PSDMR_SDA10_PBI0_A9 |\
962 PSDMR_RFRC_7_CLK |\
963 PSDMR_PRETOACT_3W |\
964 PSDMR_ACTTORW_2W |\
965 PSDMR_LDOTOPRE_1C |\
966 PSDMR_WRC_1C |\
967 PSDMR_CL_2)
968#else
969#error "INVALID SDRAM CONFIGURATION"
970#endif
971
972/*
973 * Shoot for approximately 1MHz on the prescaler.
974 */
975#if (CONFIG_8260_CLKIN >= (60 * 1000 * 1000))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200976#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV64
wdenkfe8c2802002-11-03 00:38:21 +0000977#elif (CONFIG_8260_CLKIN >= (30 * 1000 * 1000))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200978#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32
wdenkfe8c2802002-11-03 00:38:21 +0000979#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200980#warning "Unconfigured bus clock freq: check CONFIG_SYS_MPTPR and CONFIG_SYS_PSRT are OK"
981#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV32
wdenkfe8c2802002-11-03 00:38:21 +0000982#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200983#define CONFIG_SYS_PSRT 14
wdenkfe8c2802002-11-03 00:38:21 +0000984
985
986/*-----------------------------------------------------------------------
987 * BR6 - Base Register
988 * Ref: Section 10.3.1 on page 10-14
989 * OR6 - Option Register
990 * Ref: Section 10.3.2 on page 10-18
991 *-----------------------------------------------------------------------
992 */
993
994/* Bank 6 - Secondary FLASH
995 *
996 * The secondary FLASH is connected to *CS6
997 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200998#if (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE))
wdenkfe8c2802002-11-03 00:38:21 +0000999
1000/* BR6 is configured as follows:
1001 *
1002 * - Base address of 0x60000000
1003 * - 16 bit port size
1004 * - Data errors checking is disabled
1005 * - Read and write access
1006 * - GPCM 60x bus
1007 * - Access are handled by the memory controller according to MSEL
1008 * - Not used for atomic operations
1009 * - No data pipelining is done
1010 * - Valid
1011 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001012# define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_FLASH1_BASE & BRx_BA_MSK) |\
wdenkfe8c2802002-11-03 00:38:21 +00001013 BRx_PS_16 |\
1014 BRx_MS_GPCM_P |\
1015 BRx_V)
1016
1017/* OR6 is configured as follows:
1018 *
1019 * - 2 MB
1020 * - *BCTL0 is asserted upon access to the current memory bank
1021 * - *CW / *WE are negated a quarter of a clock earlier
1022 * - *CS is output at the same time as the address lines
1023 * - Uses a clock cycle length of 5
1024 * - *PSDVAL is generated internally by the memory controller
1025 * unless *GTA is asserted earlier externally.
1026 * - Relaxed timing is generated by the GPCM for accesses
1027 * initiated to this memory region.
1028 * - One idle clock is inserted between a read access from the
1029 * current bank and the next access.
1030 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001031# define CONFIG_SYS_OR6_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH1_SIZE) |\
wdenkfe8c2802002-11-03 00:38:21 +00001032 ORxG_CSNT |\
1033 ORxG_ACS_DIV1 |\
1034 ORxG_SCY_5_CLK |\
1035 ORxG_TRLX |\
1036 ORxG_EHTR)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +02001037#endif /* (defined(CONFIG_SYS_FLASH1_BASE) && defined(CONFIG_SYS_FLASH1_SIZE)) */
wdenkfe8c2802002-11-03 00:38:21 +00001038
wdenkfe8c2802002-11-03 00:38:21 +00001039#endif /* __CONFIG_H */