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Dave Liu5f820432006-11-03 19:33:44 -06001/*
2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 *
4 * Dave Liu <daveliu@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010013 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Dave Liu5f820432006-11-03 19:33:44 -060014 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21
22#ifndef __CONFIG_H
23#define __CONFIG_H
24
Dave Liu5f820432006-11-03 19:33:44 -060025/*
26 * High Level Configuration Options
27 */
28#define CONFIG_E300 1 /* E300 family */
29#define CONFIG_QE 1 /* Has QE */
Peter Tyser0f898602009-05-22 17:23:24 -050030#define CONFIG_MPC83xx 1 /* MPC83xx family */
Dave Liu5f820432006-11-03 19:33:44 -060031#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
32#define CONFIG_MPC8360EMDS 1 /* MPC8360EMDS board specific */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020033
34#define CONFIG_SYS_TEXT_BASE 0xFE000000
35
Tony Li14778582007-08-17 10:35:59 +080036#undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
37#undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */
Dave Liu5f820432006-11-03 19:33:44 -060038
39/*
40 * System Clock Setup
41 */
42#ifdef CONFIG_PCISLAVE
43#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
44#else
45#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
46#endif
47
48#ifndef CONFIG_SYS_CLK_FREQ
49#define CONFIG_SYS_CLK_FREQ 66000000
50#endif
51
52/*
53 * Hardware Reset Configuration Word
54 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055#define CONFIG_SYS_HRCW_LOW (\
Dave Liu5f820432006-11-03 19:33:44 -060056 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
57 HRCWL_DDR_TO_SCB_CLK_1X1 |\
58 HRCWL_CSB_TO_CLKIN_4X1 |\
59 HRCWL_VCO_1X2 |\
60 HRCWL_CE_PLL_VCO_DIV_4 |\
61 HRCWL_CE_PLL_DIV_1X1 |\
62 HRCWL_CE_TO_PLL_1X6 |\
63 HRCWL_CORE_TO_CSB_2X1)
64
65#ifdef CONFIG_PCISLAVE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_HRCW_HIGH (\
Dave Liu5f820432006-11-03 19:33:44 -060067 HRCWH_PCI_AGENT |\
68 HRCWH_PCI1_ARBITER_DISABLE |\
69 HRCWH_PCICKDRV_DISABLE |\
70 HRCWH_CORE_ENABLE |\
71 HRCWH_FROM_0XFFF00100 |\
72 HRCWH_BOOTSEQ_DISABLE |\
73 HRCWH_SW_WATCHDOG_DISABLE |\
74 HRCWH_ROM_LOC_LOCAL_16BIT)
75#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#define CONFIG_SYS_HRCW_HIGH (\
Dave Liu5f820432006-11-03 19:33:44 -060077 HRCWH_PCI_HOST |\
78 HRCWH_PCI1_ARBITER_ENABLE |\
79 HRCWH_PCICKDRV_ENABLE |\
80 HRCWH_CORE_ENABLE |\
81 HRCWH_FROM_0X00000100 |\
82 HRCWH_BOOTSEQ_DISABLE |\
83 HRCWH_SW_WATCHDOG_DISABLE |\
84 HRCWH_ROM_LOC_LOCAL_16BIT)
85#endif
86
87/*
88 * System IO Config
89 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_SICRH 0x00000000
91#define CONFIG_SYS_SICRL 0x40000000
Dave Liu5f820432006-11-03 19:33:44 -060092
93#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
Tony Li14778582007-08-17 10:35:59 +080094#define CONFIG_BOARD_EARLY_INIT_R
Dave Liu5f820432006-11-03 19:33:44 -060095
96/*
97 * IMMR new address
98 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_IMMR 0xE0000000
Dave Liu5f820432006-11-03 19:33:44 -0600100
101/*
102 * DDR Setup
103 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
105#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
Anton Vorontsov5c2ff322008-09-10 18:12:37 +0400106#define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* + 256M */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
108#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \
Xie Xiaobob110f402007-02-14 18:27:06 +0800109 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
Dave Liu5f820432006-11-03 19:33:44 -0600110
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_83XX_DDR_USES_CS0
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600112
Xie Xiaobob110f402007-02-14 18:27:06 +0800113#define CONFIG_DDR_ECC /* support DDR ECC function */
Dave Liu5f820432006-11-03 19:33:44 -0600114#define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
115
Xie Xiaobob110f402007-02-14 18:27:06 +0800116/*
117 * DDRCDR - DDR Control Driver Register
118 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_DDRCDR_VALUE 0x80080001
Xie Xiaobob110f402007-02-14 18:27:06 +0800120
Dave Liu5f820432006-11-03 19:33:44 -0600121#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
122#if defined(CONFIG_SPD_EEPROM)
123/*
124 * Determine DDR configuration from I2C interface.
125 */
126#define SPD_EEPROM_ADDRESS 0x52 /* DDR SODIMM */
127#else
128/*
129 * Manually set up DDR parameters
130 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_DDR_SIZE 256 /* MB */
Xie Xiaobob110f402007-02-14 18:27:06 +0800132#if defined(CONFIG_DDR_II)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_DDRCDR 0x80080001
134#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
135#define CONFIG_SYS_DDR_CS0_CONFIG 0x80330102
136#define CONFIG_SYS_DDR_TIMING_0 0x00220802
137#define CONFIG_SYS_DDR_TIMING_1 0x38357322
138#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
139#define CONFIG_SYS_DDR_TIMING_3 0x00000000
140#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
141#define CONFIG_SYS_DDR_MODE 0x47d00432
142#define CONFIG_SYS_DDR_MODE2 0x8000c000
143#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
144#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
145#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
Xie Xiaobob110f402007-02-14 18:27:06 +0800146#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
148#define CONFIG_SYS_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
149#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* may need tuning */
150#define CONFIG_SYS_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */
151#define CONFIG_SYS_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */
152#define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* page mode */
Dave Liu5f820432006-11-03 19:33:44 -0600153#endif
Xie Xiaobob110f402007-02-14 18:27:06 +0800154#endif
Dave Liu5f820432006-11-03 19:33:44 -0600155
156/*
157 * Memory test
158 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
160#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
161#define CONFIG_SYS_MEMTEST_END 0x00100000
Dave Liu5f820432006-11-03 19:33:44 -0600162
163/*
164 * The reserved memory
165 */
166
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200167#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Dave Liu5f820432006-11-03 19:33:44 -0600168
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
170#define CONFIG_SYS_RAMBOOT
Dave Liu5f820432006-11-03 19:33:44 -0600171#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#undef CONFIG_SYS_RAMBOOT
Dave Liu5f820432006-11-03 19:33:44 -0600173#endif
174
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
Kim Phillips4a9932a2009-07-07 18:04:21 -0500176#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
Dave Liu5f820432006-11-03 19:33:44 -0600178
179/*
180 * Initial RAM Base Address Setup
181 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_INIT_RAM_LOCK 1
183#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
184#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
185#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
186#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
Dave Liu5f820432006-11-03 19:33:44 -0600187
188/*
189 * Local Bus Configuration & Clock Setup
190 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500191#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
192#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_LBC_LBCR 0x00000000
Dave Liu5f820432006-11-03 19:33:44 -0600194
195/*
196 * FLASH on the Local Bus
197 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200199#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
201#define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
202#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
Jerry Van Baren82e45a22008-03-18 21:44:41 -0400203#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
Dave Liu5f820432006-11-03 19:33:44 -0600204
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
206#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
Dave Liu5f820432006-11-03 19:33:44 -0600207
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \
Dave Liu5f820432006-11-03 19:33:44 -0600209 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
210 BR_V) /* valid */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
Anton Vorontsovf9023af2008-05-29 18:14:56 +0400212 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
Xie Xiaobob110f402007-02-14 18:27:06 +0800213 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
Dave Liu5f820432006-11-03 19:33:44 -0600214
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
216#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
Dave Liu5f820432006-11-03 19:33:44 -0600217
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#undef CONFIG_SYS_FLASH_CHECKSUM
Dave Liu5f820432006-11-03 19:33:44 -0600219
220/*
221 * BCSR on the Local Bus
222 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_BCSR 0xF8000000
224#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR /* Access window base at BCSR base */
225#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000F /* Access window size 64K */
Dave Liu5f820432006-11-03 19:33:44 -0600226
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */
228#define CONFIG_SYS_OR1_PRELIM 0xFFFFE9f7 /* length 32K */
Dave Liu5f820432006-11-03 19:33:44 -0600229
230/*
231 * SDRAM on the Local Bus
232 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */
234#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
Dave Liu5f820432006-11-03 19:33:44 -0600235
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_LB_SDRAM /* if board has SRDAM on local bus */
Dave Liu5f820432006-11-03 19:33:44 -0600237
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#ifdef CONFIG_SYS_LB_SDRAM
Anton Vorontsov5c2ff322008-09-10 18:12:37 +0400239#define CONFIG_SYS_LBLAWBAR2 0
240#define CONFIG_SYS_LBLAWAR2 0x80000019 /* 64MB */
Dave Liu5f820432006-11-03 19:33:44 -0600241
242/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
243/*
244 * Base Register 2 and Option Register 2 configure SDRAM.
Dave Liu5f820432006-11-03 19:33:44 -0600245 *
246 * For BR2, need:
Anton Vorontsov5c2ff322008-09-10 18:12:37 +0400247 * Base address = BR[0:16] = dynamic
Dave Liu5f820432006-11-03 19:33:44 -0600248 * port size = 32-bits = BR2[19:20] = 11
249 * no parity checking = BR2[21:22] = 00
250 * SDRAM for MSEL = BR2[24:26] = 011
251 * Valid = BR[31] = 1
252 *
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100253 * 0 4 8 12 16 20 24 28
Anton Vorontsov5c2ff322008-09-10 18:12:37 +0400254 * xxxx xxxx xxxx xxxx x001 1000 0110 0001 = 00001861
Dave Liu5f820432006-11-03 19:33:44 -0600255 */
256
Anton Vorontsov5c2ff322008-09-10 18:12:37 +0400257#define CONFIG_SYS_BR2 0x00001861 /*Port size=32bit, MSEL=SDRAM */
Dave Liu5f820432006-11-03 19:33:44 -0600258
259/*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
Dave Liu5f820432006-11-03 19:33:44 -0600261 *
262 * For OR2, need:
263 * 64MB mask for AM, OR2[0:7] = 1111 1100
264 * XAM, OR2[17:18] = 11
265 * 9 columns OR2[19-21] = 010
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100266 * 13 rows OR2[23-25] = 100
Dave Liu5f820432006-11-03 19:33:44 -0600267 * EAD set for extra time OR[31] = 1
268 *
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100269 * 0 4 8 12 16 20 24 28
Dave Liu5f820432006-11-03 19:33:44 -0600270 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
271 */
272
Anton Vorontsov5c2ff322008-09-10 18:12:37 +0400273#define CONFIG_SYS_OR2 0xfc006901
Dave Liu5f820432006-11-03 19:33:44 -0600274
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */
276#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */
Dave Liu5f820432006-11-03 19:33:44 -0600277
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723
Dave Liu5f820432006-11-03 19:33:44 -0600279
280/*
281 * SDRAM Controller configuration sequence.
282 */
Kumar Gala540dcf12009-03-26 01:34:39 -0500283#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
284#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
285#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
286#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
287#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
Dave Liu5f820432006-11-03 19:33:44 -0600288
289#endif
290
291/*
292 * Windows to access PIB via local bus
293 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_LBLAWBAR3_PRELIM 0xf8010000 /* windows base 0xf8010000 */
295#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000e /* windows size 32KB */
Dave Liu5f820432006-11-03 19:33:44 -0600296
297/*
298 * CS4 on Local Bus, to PIB
299 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_BR4_PRELIM 0xf8010801 /* CS4 base address at 0xf8010000 */
301#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
Dave Liu5f820432006-11-03 19:33:44 -0600302
303/*
304 * CS5 on Local Bus, to PIB
305 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_BR5_PRELIM 0xf8008801 /* CS5 base address at 0xf8008000 */
307#define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
Dave Liu5f820432006-11-03 19:33:44 -0600308
309/*
310 * Serial Port
311 */
312#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_NS16550
314#define CONFIG_SYS_NS16550_SERIAL
315#define CONFIG_SYS_NS16550_REG_SIZE 1
316#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Dave Liu5f820432006-11-03 19:33:44 -0600317
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318#define CONFIG_SYS_BAUDRATE_TABLE \
Dave Liu5f820432006-11-03 19:33:44 -0600319 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
320
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
322#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Dave Liu5f820432006-11-03 19:33:44 -0600323
Kim Phillips22d71a72007-02-27 18:41:08 -0600324#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Kim Phillipsa059e902010-04-15 17:36:05 -0500325#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Dave Liu5f820432006-11-03 19:33:44 -0600326/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_HUSH_PARSER
328#ifdef CONFIG_SYS_HUSH_PARSER
329#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Dave Liu5f820432006-11-03 19:33:44 -0600330#endif
331
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600332/* pass open firmware flat tree */
Gerald Van Baren213bf8c2007-03-31 12:23:51 -0400333#define CONFIG_OF_LIBFDT 1
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600334#define CONFIG_OF_BOARD_SETUP 1
Kim Phillips5b8bc602007-12-20 14:09:22 -0600335#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600336
Dave Liu5f820432006-11-03 19:33:44 -0600337/* I2C */
338#define CONFIG_HARD_I2C /* I2C with hardware support */
339#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Timur Tabibe5e6182006-11-03 19:15:00 -0600340#define CONFIG_FSL_I2C
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
342#define CONFIG_SYS_I2C_SLAVE 0x7F
343#define CONFIG_SYS_I2C_NOPROBES {0x52} /* Don't probe these addrs */
344#define CONFIG_SYS_I2C_OFFSET 0x3000
345#define CONFIG_SYS_I2C2_OFFSET 0x3100
Dave Liu5f820432006-11-03 19:33:44 -0600346
347/*
348 * Config on-board RTC
349 */
350#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Dave Liu5f820432006-11-03 19:33:44 -0600352
353/*
354 * General PCI
355 * Addresses are mapped 1-1.
356 */
Kim Phillips9993e192009-07-18 18:42:13 -0500357#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
358#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
359#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
360#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
361#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
362#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
363#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
364#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
365#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
Dave Liu5f820432006-11-03 19:33:44 -0600366
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
368#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
369#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
Dave Liu5f820432006-11-03 19:33:44 -0600370
371
372#ifdef CONFIG_PCI
373
374#define CONFIG_NET_MULTI
375#define CONFIG_PCI_PNP /* do pci plug-and-play */
Kim Phillips9993e192009-07-18 18:42:13 -0500376#define CONFIG_83XX_PCI_STREAMING
Dave Liu5f820432006-11-03 19:33:44 -0600377
378#undef CONFIG_EEPRO100
379#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200380#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
Dave Liu5f820432006-11-03 19:33:44 -0600381
382#endif /* CONFIG_PCI */
383
384
385#ifndef CONFIG_NET_MULTI
386#define CONFIG_NET_MULTI 1
387#endif
388
Anton Vorontsovda6eea02009-09-16 23:22:08 +0400389#define CONFIG_HWCONFIG 1
390
Dave Liu5f820432006-11-03 19:33:44 -0600391/*
Dave Liu7737d5c2006-11-03 12:11:15 -0600392 * QE UEC ethernet configuration
393 */
394#define CONFIG_UEC_ETH
Kim Phillips78b7a8e2010-07-26 18:34:57 -0500395#define CONFIG_ETHPRIME "UEC0"
Dave Liu7737d5c2006-11-03 12:11:15 -0600396#define CONFIG_PHY_MODE_NEED_CHANGE
397
398#define CONFIG_UEC_ETH1 /* GETH1 */
399
400#ifdef CONFIG_UEC_ETH1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200401#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
402#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
403#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9
404#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
405#define CONFIG_SYS_UEC1_PHY_ADDR 0
Heiko Schocher582c55a2010-01-20 09:04:28 +0100406#define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID
407#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
Dave Liu7737d5c2006-11-03 12:11:15 -0600408#endif
409
410#define CONFIG_UEC_ETH2 /* GETH2 */
411
412#ifdef CONFIG_UEC_ETH2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200413#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
414#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
415#define CONFIG_SYS_UEC2_TX_CLK QE_CLK4
416#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
417#define CONFIG_SYS_UEC2_PHY_ADDR 1
Heiko Schocher582c55a2010-01-20 09:04:28 +0100418#define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID
419#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
Dave Liu7737d5c2006-11-03 12:11:15 -0600420#endif
421
422/*
Dave Liu5f820432006-11-03 19:33:44 -0600423 * Environment
424 */
425
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200426#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200427 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200428 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200429 #define CONFIG_ENV_SECT_SIZE 0x20000
430 #define CONFIG_ENV_SIZE 0x2000
Dave Liu5f820432006-11-03 19:33:44 -0600431#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200432 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200433 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200434 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200435 #define CONFIG_ENV_SIZE 0x2000
Dave Liu5f820432006-11-03 19:33:44 -0600436#endif
437
438#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200439#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Dave Liu5f820432006-11-03 19:33:44 -0600440
Jon Loeliger8ea54992007-07-04 22:30:06 -0500441/*
Jon Loeliger659e2f62007-07-10 09:10:49 -0500442 * BOOTP options
443 */
444#define CONFIG_BOOTP_BOOTFILESIZE
445#define CONFIG_BOOTP_BOOTPATH
446#define CONFIG_BOOTP_GATEWAY
447#define CONFIG_BOOTP_HOSTNAME
448
449
450/*
Jon Loeliger8ea54992007-07-04 22:30:06 -0500451 * Command line configuration.
452 */
453#include <config_cmd_default.h>
454
455#define CONFIG_CMD_PING
456#define CONFIG_CMD_I2C
457#define CONFIG_CMD_ASKENV
Jerry Van Barenb5cdd7d2008-01-12 13:24:14 -0500458#define CONFIG_CMD_SDRAM
Jon Loeliger8ea54992007-07-04 22:30:06 -0500459
Dave Liu5f820432006-11-03 19:33:44 -0600460#if defined(CONFIG_PCI)
Jon Loeliger8ea54992007-07-04 22:30:06 -0500461 #define CONFIG_CMD_PCI
Dave Liu5f820432006-11-03 19:33:44 -0600462#endif
463
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200464#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500465 #undef CONFIG_CMD_SAVEENV
Jon Loeliger8ea54992007-07-04 22:30:06 -0500466 #undef CONFIG_CMD_LOADS
467#endif
468
Dave Liu5f820432006-11-03 19:33:44 -0600469
470#undef CONFIG_WATCHDOG /* watchdog disabled */
471
472/*
473 * Miscellaneous configurable options
474 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200475#define CONFIG_SYS_LONGHELP /* undef to save memory */
476#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
477#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Dave Liu5f820432006-11-03 19:33:44 -0600478
Jon Loeliger8ea54992007-07-04 22:30:06 -0500479#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200480 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Dave Liu5f820432006-11-03 19:33:44 -0600481#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200482 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Dave Liu5f820432006-11-03 19:33:44 -0600483#endif
484
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200485#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
486#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
487#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
488#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Dave Liu5f820432006-11-03 19:33:44 -0600489
490/*
491 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700492 * have to be in the first 256 MB of memory, since this is
Dave Liu5f820432006-11-03 19:33:44 -0600493 * the maximum mapped by the Linux kernel during initialization.
494 */
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700495#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
Dave Liu5f820432006-11-03 19:33:44 -0600496
497/*
498 * Core HID Setup
499 */
Kim Phillips1a2e2032010-04-20 19:37:54 -0500500#define CONFIG_SYS_HID0_INIT 0x000000000
501#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
502 HID0_ENABLE_INSTRUCTION_CACHE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200503#define CONFIG_SYS_HID2 HID2_HBE
Dave Liu5f820432006-11-03 19:33:44 -0600504
505/*
Dave Liu5f820432006-11-03 19:33:44 -0600506 * MMU Setup
507 */
508
Becky Bruce31d82672008-05-08 19:02:12 -0500509#define CONFIG_HIGH_BATS 1 /* High BATs supported */
510
Anton Vorontsov5c2ff322008-09-10 18:12:37 +0400511/* DDR/LBC SDRAM: cacheable */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200512#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
513#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
514#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
515#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
Dave Liu5f820432006-11-03 19:33:44 -0600516
517/* IMMRBAR & PCI IO: cache-inhibit and guarded */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200518#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \
Dave Liu5f820432006-11-03 19:33:44 -0600519 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200520#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
521#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
522#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
Dave Liu5f820432006-11-03 19:33:44 -0600523
524/* BCSR: cache-inhibit and guarded */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200525#define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR | BATL_PP_10 | \
Dave Liu5f820432006-11-03 19:33:44 -0600526 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200527#define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
528#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
529#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
Dave Liu5f820432006-11-03 19:33:44 -0600530
531/* FLASH: icache cacheable, but dcache-inhibit and guarded */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200532#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
533#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
534#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
Dave Liu5f820432006-11-03 19:33:44 -0600535 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200536#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
Dave Liu5f820432006-11-03 19:33:44 -0600537
Anton Vorontsov5c2ff322008-09-10 18:12:37 +0400538/* DDR/LBC SDRAM next 256M: cacheable */
539#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM_BASE2 | BATL_PP_10 | BATL_MEMCOHERENCE)
540#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM_BASE2 | BATU_BL_256M | BATU_VS | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200541#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
542#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
Dave Liu5f820432006-11-03 19:33:44 -0600543
544/* Stack in dcache: cacheable, no memory coherence */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200545#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
546#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
547#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
548#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
Dave Liu5f820432006-11-03 19:33:44 -0600549
550#ifdef CONFIG_PCI
551/* PCI MEM space: cacheable */
Kim Phillips9993e192009-07-18 18:42:13 -0500552#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
553#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200554#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
555#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
Dave Liu5f820432006-11-03 19:33:44 -0600556/* PCI MMIO space: cache-inhibit and guarded */
Kim Phillips9993e192009-07-18 18:42:13 -0500557#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \
Dave Liu5f820432006-11-03 19:33:44 -0600558 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Kim Phillips9993e192009-07-18 18:42:13 -0500559#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200560#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
561#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Dave Liu5f820432006-11-03 19:33:44 -0600562#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200563#define CONFIG_SYS_IBAT6L (0)
564#define CONFIG_SYS_IBAT6U (0)
565#define CONFIG_SYS_IBAT7L (0)
566#define CONFIG_SYS_IBAT7U (0)
567#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
568#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
569#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
570#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Dave Liu5f820432006-11-03 19:33:44 -0600571#endif
572
Jon Loeliger8ea54992007-07-04 22:30:06 -0500573#if defined(CONFIG_CMD_KGDB)
Dave Liu5f820432006-11-03 19:33:44 -0600574#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
575#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
576#endif
577
578/*
579 * Environment Configuration
580 */
581
582#define CONFIG_ENV_OVERWRITE
583
584#if defined(CONFIG_UEC_ETH)
Kim Phillips977b5752008-01-09 15:24:06 -0600585#define CONFIG_HAS_ETH0
Dave Liu5f820432006-11-03 19:33:44 -0600586#define CONFIG_HAS_ETH1
Dave Liu5f820432006-11-03 19:33:44 -0600587#endif
588
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100589#define CONFIG_BAUDRATE 115200
Dave Liu5f820432006-11-03 19:33:44 -0600590
Kim Phillips79f516b2009-08-21 16:34:38 -0500591#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
Dave Liu5f820432006-11-03 19:33:44 -0600592
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100593#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
594#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
Dave Liu5f820432006-11-03 19:33:44 -0600595
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100596#define CONFIG_EXTRA_ENV_SETTINGS \
597 "netdev=eth0\0" \
598 "consoledev=ttyS0\0" \
599 "ramdiskaddr=1000000\0" \
Dave Liu5f820432006-11-03 19:33:44 -0600600 "ramdiskfile=ramfs.83xx\0" \
Kim Phillips79f516b2009-08-21 16:34:38 -0500601 "fdtaddr=780000\0" \
Kim Phillips270fe262008-03-07 12:27:31 -0600602 "fdtfile=mpc836x_mds.dtb\0" \
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600603 ""
Dave Liu5f820432006-11-03 19:33:44 -0600604
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100605#define CONFIG_NFSBOOTCOMMAND \
606 "setenv bootargs root=/dev/nfs rw " \
607 "nfsroot=$serverip:$rootpath " \
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600608 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100609 "console=$consoledev,$baudrate $othbootargs;" \
610 "tftp $loadaddr $bootfile;" \
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600611 "tftp $fdtaddr $fdtfile;" \
612 "bootm $loadaddr - $fdtaddr"
Dave Liu5f820432006-11-03 19:33:44 -0600613
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600614#define CONFIG_RAMBOOTCOMMAND \
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100615 "setenv bootargs root=/dev/ram rw " \
616 "console=$consoledev,$baudrate $othbootargs;" \
617 "tftp $ramdiskaddr $ramdiskfile;" \
618 "tftp $loadaddr $bootfile;" \
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600619 "tftp $fdtaddr $fdtfile;" \
620 "bootm $loadaddr $ramdiskaddr $fdtaddr"
621
Dave Liu5f820432006-11-03 19:33:44 -0600622
623#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
624
625#endif /* __CONFIG_H */