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TsiChungLiewe2756f42008-01-14 17:47:23 -06001/*
2 * MCF5227x Internal Memory Map
3 *
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
TsiChungLiewe2756f42008-01-14 17:47:23 -06008 */
9
10#ifndef __MCF5227X__
11#define __MCF5227X__
12
TsiChung Liew012522f2008-10-21 10:03:07 +000013/* Interrupt Controller (INTC) */
TsiChungLiewe2756f42008-01-14 17:47:23 -060014#define INT0_LO_RSVD0 (0)
15#define INT0_LO_EPORT1 (1)
16#define INT0_LO_EPORT4 (4)
17#define INT0_LO_EPORT7 (7)
18#define INT0_LO_EDMA_00 (8)
19#define INT0_LO_EDMA_01 (9)
20#define INT0_LO_EDMA_02 (10)
21#define INT0_LO_EDMA_03 (11)
22#define INT0_LO_EDMA_04 (12)
23#define INT0_LO_EDMA_05 (13)
24#define INT0_LO_EDMA_06 (14)
25#define INT0_LO_EDMA_07 (15)
26#define INT0_LO_EDMA_08 (16)
27#define INT0_LO_EDMA_09 (17)
28#define INT0_LO_EDMA_10 (18)
29#define INT0_LO_EDMA_11 (19)
30#define INT0_LO_EDMA_12 (20)
31#define INT0_LO_EDMA_13 (21)
32#define INT0_LO_EDMA_14 (22)
33#define INT0_LO_EDMA_15 (23)
34#define INT0_LO_EDMA_ERR (24)
35#define INT0_LO_SCM_CWIC (25)
36#define INT0_LO_UART0 (26)
37#define INT0_LO_UART1 (27)
38#define INT0_LO_UART2 (28)
39#define INT0_LO_I2C (30)
40#define INT0_LO_DSPI (31)
41#define INT0_HI_DTMR0 (32)
42#define INT0_HI_DTMR1 (33)
43#define INT0_HI_DTMR2 (34)
44#define INT0_HI_DTMR3 (35)
45#define INT0_HI_SCMIR (62)
46#define INT0_HI_RTC_ISR (63)
47
48#define INT1_HI_CAN_BOFFINT (1)
49#define INT1_HI_CAN_ERRINT (3)
50#define INT1_HI_CAN_BUF0I (4)
51#define INT1_HI_CAN_BUF1I (5)
52#define INT1_HI_CAN_BUF2I (6)
53#define INT1_HI_CAN_BUF3I (7)
54#define INT1_HI_CAN_BUF4I (8)
55#define INT1_HI_CAN_BUF5I (9)
56#define INT1_HI_CAN_BUF6I (10)
57#define INT1_HI_CAN_BUF7I (11)
58#define INT1_HI_CAN_BUF8I (12)
59#define INT1_HI_CAN_BUF9I (13)
60#define INT1_HI_CAN_BUF10I (14)
61#define INT1_HI_CAN_BUF11I (15)
62#define INT1_HI_CAN_BUF12I (16)
63#define INT1_HI_CAN_BUF13I (17)
64#define INT1_HI_CAN_BUF14I (18)
65#define INT1_HI_CAN_BUF15I (19)
66#define INT1_HI_PIT0_PIF (43)
67#define INT1_HI_PIT1_PIF (44)
68#define INT1_HI_USBOTG_STS (47)
69#define INT1_HI_SSI_ISR (49)
70#define INT1_HI_PWM_INT (50)
71#define INT1_HI_LCDC_ISR (51)
72#define INT1_HI_CCM_UOCSR (53)
73#define INT1_HI_DSPI_EOQF (54)
74#define INT1_HI_DSPI_TFFF (55)
75#define INT1_HI_DSPI_TCF (56)
76#define INT1_HI_DSPI_TFUF (57)
77#define INT1_HI_DSPI_RFDF (58)
78#define INT1_HI_DSPI_RFOF (59)
79#define INT1_HI_DSPI_RFOF_TFUF (60)
80#define INT1_HI_TOUCH_ADC (61)
81#define INT1_HI_PLL_LOCKS (62)
82
TsiChungLiewe2756f42008-01-14 17:47:23 -060083/*********************************************************************
84* Reset Controller Module (RCM)
85*********************************************************************/
86
87/* Bit definitions and macros for RCR */
88#define RCM_RCR_FRCRSTOUT (0x40)
89#define RCM_RCR_SOFTRST (0x80)
90
91/* Bit definitions and macros for RSR */
92#define RCM_RSR_LOL (0x01)
93#define RCM_RSR_WDR_CORE (0x02)
94#define RCM_RSR_EXT (0x04)
95#define RCM_RSR_POR (0x08)
96#define RCM_RSR_SOFT (0x20)
97
98/*********************************************************************
99* Chip Configuration Module (CCM)
100*********************************************************************/
101
102/* Bit definitions and macros for CCR */
103#define CCM_CCR_DRAMSEL (0x0100)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600104#define CCM_CCR_CSC_UNMASK (0xFF3F)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600105#define CCM_CCR_CSC_FBCS5_CS4 (0x00C0)
106#define CCM_CCR_CSC_FBCS5_A22 (0x0080)
107#define CCM_CCR_CSC_FB_A23_A22 (0x0040)
108#define CCM_CCR_LIMP (0x0020)
109#define CCM_CCR_LOAD (0x0010)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600110#define CCM_CCR_BOOTPS_UNMASK (0xFFF3)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600111#define CCM_CCR_BOOTPS_PS16 (0x0008)
112#define CCM_CCR_BOOTPS_PS8 (0x0004)
113#define CCM_CCR_BOOTPS_PS32 (0x0000)
114#define CCM_CCR_OSCMODE_OSCBYPASS (0x0002)
115
116/* Bit definitions and macros for RCON */
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600117#define CCM_RCON_CSC_UNMASK (0xFF3F)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600118#define CCM_RCON_CSC_FBCS5_CS4 (0x00C0)
119#define CCM_RCON_CSC_FBCS5_A22 (0x0080)
120#define CCM_RCON_CSC_FB_A23_A22 (0x0040)
121#define CCM_RCON_LIMP (0x0020)
122#define CCM_RCON_LOAD (0x0010)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600123#define CCM_RCON_BOOTPS_UNMASK (0xFFF3)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600124#define CCM_RCON_BOOTPS_PS16 (0x0008)
125#define CCM_RCON_BOOTPS_PS8 (0x0004)
126#define CCM_RCON_BOOTPS_PS32 (0x0000)
127#define CCM_RCON_OSCMODE_OSCBYPASS (0x0002)
128
129/* Bit definitions and macros for CIR */
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600130#define CCM_CIR_PIN(x) (((x) & 0xFFC0) >> 6)
131#define CCM_CIR_PRN(x) ((x) & 0x003F)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600132#define CCM_CIR_PIN_MCF52277 (0x0000)
133
134/* Bit definitions and macros for MISCCR */
135#define CCM_MISCCR_RTCSRC (0x4000)
136#define CCM_MISCCR_USBPUE (0x2000) /* USB transceiver pull-up */
137#define CCM_MISCCR_LIMP (0x1000) /* Limp mode enable */
138
139#define CCM_MISCCR_BME (0x0800) /* Bus monitor ext en bit */
140#define CCM_MISCCR_BMT_65536 (0)
141#define CCM_MISCCR_BMT_32768 (1)
142#define CCM_MISCCR_BMT_16384 (2)
143#define CCM_MISCCR_BMT_8192 (3)
144#define CCM_MISCCR_BMT_4096 (4)
145#define CCM_MISCCR_BMT_2048 (5)
146#define CCM_MISCCR_BMT_1024 (6)
147#define CCM_MISCCR_BMT_512 (7)
148
149#define CCM_MISCCR_SSIPUE (0x0080) /* SSI RXD/TXD pull enable */
150#define CCM_MISCCR_SSIPUS (0x0040) /* SSI RXD/TXD pull select */
151#define CCM_MISCCR_TIMDMA (0x0020) /* Timer DMA mux selection */
152#define CCM_MISCCR_SSISRC (0x0010) /* SSI clock source */
153#define CCM_MISCCR_LCDCHEN (0x0004) /* LCD Int CLK en */
154#define CCM_MISCCR_USBOC (0x0002) /* USB VBUS over-current sense pol */
155#define CCM_MISCCR_USBSRC (0x0001) /* USB clock source */
156
157/* Bit definitions and macros for CDR */
158#define CCM_CDR_USBDIV(x) (((x)&0x0003)<<12)
159#define CCM_CDR_LPDIV(x) (((x)&0x000F)<<8) /* Low power clk div */
160#define CCM_CDR_SSIDIV(x) (((x)&0x00FF)) /* SSI oversampling clk div */
161
162/* Bit definitions and macros for UOCSR */
163#define CCM_UOCSR_DPPD (0x2000) /* D+ 15Kohm pull-down (rd-only) */
164#define CCM_UOCSR_DMPD (0x1000) /* D- 15Kohm pull-down (rd-only) */
165#define CCM_UOCSR_CRG_VBUS (0x0400) /* VBUS charge resistor enabled (rd-only) */
166#define CCM_UOCSR_DCR_VBUS (0x0200) /* VBUS discharge resistor en (rd-only) */
167#define CCM_UOCSR_DPPU (0x0100) /* D+ pull-up for FS enabled (rd-only) */
168#define CCM_UOCSR_AVLD (0x0080) /* A-peripheral valid indicator */
169#define CCM_UOCSR_BVLD (0x0040) /* B-peripheral valid indicator */
170#define CCM_UOCSR_VVLD (0x0020) /* VBUS valid indicator */
171#define CCM_UOCSR_SEND (0x0010) /* Session end */
172#define CCM_UOCSR_WKUP (0x0004) /* USB OTG controller wake-up event */
173#define CCM_UOCSR_UOMIE (0x0002) /* USB OTG misc interrupt en */
174#define CCM_UOCSR_XPDE (0x0001) /* On-chip transceiver pull-down en */
175
176/*********************************************************************
177* General Purpose I/O Module (GPIO)
178*********************************************************************/
179/* Bit definitions and macros for PAR_BE */
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600180#define GPIO_PAR_BE_UNMASK (0x0F)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600181#define GPIO_PAR_BE_BE3_BE3 (0x08)
182#define GPIO_PAR_BE_BE3_GPIO (0x00)
183#define GPIO_PAR_BE_BE2_BE2 (0x04)
184#define GPIO_PAR_BE_BE2_GPIO (0x00)
185#define GPIO_PAR_BE_BE1_BE1 (0x02)
186#define GPIO_PAR_BE_BE1_GPIO (0x00)
187#define GPIO_PAR_BE_BE0_BE0 (0x01)
188#define GPIO_PAR_BE_BE0_GPIO (0x00)
189
190/* Bit definitions and macros for PAR_CS */
191#define GPIO_PAR_CS_CS3 (0x10)
192#define GPIO_PAR_CS_CS2 (0x08)
193#define GPIO_PAR_CS_CS1_FBCS1 (0x06)
194#define GPIO_PAR_CS_CS1_SDCS1 (0x04)
195#define GPIO_PAR_CS_CS1_GPIO (0x00)
196#define GPIO_PAR_CS_CS0 (0x01)
197
198/* Bit definitions and macros for PAR_FBCTL */
199#define GPIO_PAR_FBCTL_OE (0x80)
200#define GPIO_PAR_FBCTL_TA (0x40)
201#define GPIO_PAR_FBCTL_RW (0x20)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600202#define GPIO_PAR_FBCTL_TS_UNMASK (0xE7)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600203#define GPIO_PAR_FBCTL_TS_FBTS (0x18)
204#define GPIO_PAR_FBCTL_TS_DMAACK (0x10)
205#define GPIO_PAR_FBCTL_TS_GPIO (0x00)
206
207/* Bit definitions and macros for PAR_FECI2C */
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600208#define GPIO_PAR_I2C_SCL_UNMASK (0xF3)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600209#define GPIO_PAR_I2C_SCL_SCL (0x0C)
210#define GPIO_PAR_I2C_SCL_CANTXD (0x08)
211#define GPIO_PAR_I2C_SCL_U2TXD (0x04)
212#define GPIO_PAR_I2C_SCL_GPIO (0x00)
213
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600214#define GPIO_PAR_I2C_SDA_UNMASK (0xFC)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600215#define GPIO_PAR_I2C_SDA_SDA (0x03)
216#define GPIO_PAR_I2C_SDA_CANRXD (0x02)
217#define GPIO_PAR_I2C_SDA_U2RXD (0x01)
218#define GPIO_PAR_I2C_SDA_GPIO (0x00)
219
220/* Bit definitions and macros for PAR_UART */
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600221#define GPIO_PAR_UART_U1CTS_UNMASK (0x3FFF)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600222#define GPIO_PAR_UART_U1CTS_U1CTS (0xC000)
223#define GPIO_PAR_UART_U1CTS_SSIBCLK (0x8000)
224#define GPIO_PAR_UART_U1CTS_LCDCLS (0x4000)
225#define GPIO_PAR_UART_U1CTS_GPIO (0x0000)
226
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600227#define GPIO_PAR_UART_U1RTS_UNMASK (0xCFFF)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600228#define GPIO_PAR_UART_U1RTS_U1RTS (0x3000)
229#define GPIO_PAR_UART_U1RTS_SSIFS (0x2000)
230#define GPIO_PAR_UART_U1RTS_LCDPS (0x1000)
231#define GPIO_PAR_UART_U1RTS_GPIO (0x0000)
232
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600233#define GPIO_PAR_UART_U1RXD_UNMASK (0xF3FF)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600234#define GPIO_PAR_UART_U1RXD_U1RXD (0x0C00)
235#define GPIO_PAR_UART_U1RXD_SSIRXD (0x0800)
236#define GPIO_PAR_UART_U1RXD_GPIO (0x0000)
237
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600238#define GPIO_PAR_UART_U1TXD_UNMASK (0xFCFF)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600239#define GPIO_PAR_UART_U1TXD_U1TXD (0x0300)
240#define GPIO_PAR_UART_U1TXD_SSITXD (0x0200)
241#define GPIO_PAR_UART_U1TXD_GPIO (0x0000)
242
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600243#define GPIO_PAR_UART_U0CTS_UNMASK (0xFF3F)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600244#define GPIO_PAR_UART_U0CTS_U0CTS (0x00C0)
245#define GPIO_PAR_UART_U0CTS_T1OUT (0x0080)
246#define GPIO_PAR_UART_U0CTS_USBVBUSEN (0x0040)
247#define GPIO_PAR_UART_U0CTS_GPIO (0x0000)
248
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600249#define GPIO_PAR_UART_U0RTS_UNMASK (0xFFCF)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600250#define GPIO_PAR_UART_U0RTS_U0RTS (0x0030)
251#define GPIO_PAR_UART_U0RTS_T1IN (0x0020)
252#define GPIO_PAR_UART_U0RTS_USBVBUSOC (0x0010)
253#define GPIO_PAR_UART_U0RTS_GPIO (0x0000)
254
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600255#define GPIO_PAR_UART_U0RXD_UNMASK (0xFFF3)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600256#define GPIO_PAR_UART_U0RXD_U0RXD (0x000C)
257#define GPIO_PAR_UART_U0RXD_CANRX (0x0008)
258#define GPIO_PAR_UART_U0RXD_GPIO (0x0000)
259
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600260#define GPIO_PAR_UART_U0TXD_UNMASK (0xFFFC)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600261#define GPIO_PAR_UART_U0TXD_U0TXD (0x0003)
262#define GPIO_PAR_UART_U0TXD_CANTX (0x0002)
263#define GPIO_PAR_UART_U0TXD_GPIO (0x0000)
264
265/* Bit definitions and macros for PAR_DSPI */
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600266#define GPIO_PAR_DSPI_PCS0_UNMASK (0x3F)
TsiChung Liewa21d0c22008-10-21 15:37:02 +0000267#define GPIO_PAR_DSPI_PCS0_PCS0 (0xC0)
268#define GPIO_PAR_DSPI_PCS0_U2RTS (0x80)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600269#define GPIO_PAR_DSPI_PCS0_GPIO (0x00)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600270#define GPIO_PAR_DSPI_SIN_UNMASK (0xCF)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600271#define GPIO_PAR_DSPI_SIN_SIN (0x30)
272#define GPIO_PAR_DSPI_SIN_U2RXD (0x20)
273#define GPIO_PAR_DSPI_SIN_GPIO (0x00)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600274#define GPIO_PAR_DSPI_SOUT_UNMASK (0xF3)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600275#define GPIO_PAR_DSPI_SOUT_SOUT (0x0C)
276#define GPIO_PAR_DSPI_SOUT_U2TXD (0x08)
277#define GPIO_PAR_DSPI_SOUT_GPIO (0x00)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600278#define GPIO_PAR_DSPI_SCK_UNMASK (0xFC)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600279#define GPIO_PAR_DSPI_SCK_SCK (0x03)
280#define GPIO_PAR_DSPI_SCK_U2CTS (0x02)
281#define GPIO_PAR_DSPI_SCK_GPIO (0x00)
282
283/* Bit definitions and macros for PAR_TIMER */
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600284#define GPIO_PAR_TIMER_T3IN_UNMASK (0x3F)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600285#define GPIO_PAR_TIMER_T3IN_T3IN (0xC0)
286#define GPIO_PAR_TIMER_T3IN_T3OUT (0x80)
287#define GPIO_PAR_TIMER_T3IN_SSIMCLK (0x40)
288#define GPIO_PAR_TIMER_T3IN_GPIO (0x00)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600289#define GPIO_PAR_TIMER_T2IN_UNMASK (0xCF)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600290#define GPIO_PAR_TIMER_T2IN_T2IN (0x30)
291#define GPIO_PAR_TIMER_T2IN_T2OUT (0x20)
292#define GPIO_PAR_TIMER_T2IN_DSPIPCS2 (0x10)
293#define GPIO_PAR_TIMER_T2IN_GPIO (0x00)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600294#define GPIO_PAR_TIMER_T1IN_UNMASK (0xF3)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600295#define GPIO_PAR_TIMER_T1IN_T1IN (0x0C)
296#define GPIO_PAR_TIMER_T1IN_T1OUT (0x08)
297#define GPIO_PAR_TIMER_T1IN_LCDCONTRAST (0x04)
298#define GPIO_PAR_TIMER_T1IN_GPIO (0x00)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600299#define GPIO_PAR_TIMER_T0IN_UNMASK (0xFC)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600300#define GPIO_PAR_TIMER_T0IN_T0IN (0x03)
301#define GPIO_PAR_TIMER_T0IN_T0OUT (0x02)
302#define GPIO_PAR_TIMER_T0IN_LCDREV (0x01)
303#define GPIO_PAR_TIMER_T0IN_GPIO (0x00)
304
305/* Bit definitions and macros for GPIO_PAR_LCDCTL */
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600306#define GPIO_PAR_LCDCTL_ACDOE_UNMASK (0xE7)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600307#define GPIO_PAR_LCDCTL_ACDOE_ACDOE (0x18)
308#define GPIO_PAR_LCDCTL_ACDOE_SPLSPR (0x10)
309#define GPIO_PAR_LCDCTL_ACDOE_GPIO (0x00)
310#define GPIO_PAR_LCDCTL_FLM_VSYNC (0x04)
311#define GPIO_PAR_LCDCTL_LP_HSYNC (0x02)
312#define GPIO_PAR_LCDCTL_LSCLK (0x01)
313
314/* Bit definitions and macros for PAR_IRQ */
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600315#define GPIO_PAR_IRQ_IRQ4_UNMASK (0xF3)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600316#define GPIO_PAR_IRQ_IRQ4_SSIINPCLK (0x0C)
317#define GPIO_PAR_IRQ_IRQ4_DMAREQ0 (0x08)
318#define GPIO_PAR_IRQ_IRQ4_GPIO (0x00)
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600319#define GPIO_PAR_IRQ_IRQ1_UNMASK (0xFC)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600320#define GPIO_PAR_IRQ_IRQ1_PCIINT (0x03)
321#define GPIO_PAR_IRQ_IRQ1_USBCLKIN (0x02)
322#define GPIO_PAR_IRQ_IRQ1_SSICLKIN (0x01)
323#define GPIO_PAR_IRQ_IRQ1_GPIO (0x00)
324
325/* Bit definitions and macros for GPIO_PAR_LCDH */
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600326#define GPIO_PAR_LCDH_LD17_UNMASK (0xFFFFF3FF)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600327#define GPIO_PAR_LCDH_LD17_LD17 (0x00000C00)
328#define GPIO_PAR_LCDH_LD17_LD11 (0x00000800)
329#define GPIO_PAR_LCDH_LD17_GPIO (0x00000000)
330
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600331#define GPIO_PAR_LCDH_LD16_UNMASK (0xFFFFFCFF)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600332#define GPIO_PAR_LCDH_LD16_LD16 (0x00000300)
333#define GPIO_PAR_LCDH_LD16_LD10 (0x00000200)
334#define GPIO_PAR_LCDH_LD16_GPIO (0x00000000)
335
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600336#define GPIO_PAR_LCDH_LD15_UNMASK (0xFFFFFF3F)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600337#define GPIO_PAR_LCDH_LD15_LD15 (0x000000C0)
338#define GPIO_PAR_LCDH_LD15_LD9 (0x00000080)
339#define GPIO_PAR_LCDH_LD15_GPIO (0x00000000)
340
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600341#define GPIO_PAR_LCDH_LD14_UNMASK (0xFFFFFFCF)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600342#define GPIO_PAR_LCDH_LD14_LD14 (0x00000030)
343#define GPIO_PAR_LCDH_LD14_LD8 (0x00000020)
344#define GPIO_PAR_LCDH_LD14_GPIO (0x00000000)
345
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600346#define GPIO_PAR_LCDH_LD13_UNMASK (0xFFFFFFF3)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600347#define GPIO_PAR_LCDH_LD13_LD13 (0x0000000C)
348#define GPIO_PAR_LCDH_LD13_CANTX (0x00000008)
349#define GPIO_PAR_LCDH_LD13_GPIO (0x00000000)
350
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600351#define GPIO_PAR_LCDH_LD12_UNMASK (0xFFFFFFFC)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600352#define GPIO_PAR_LCDH_LD12_LD12 (0x00000003)
353#define GPIO_PAR_LCDH_LD12_CANRX (0x00000002)
354#define GPIO_PAR_LCDH_LD12_GPIO (0x00000000)
355
356/* Bit definitions and macros for GPIO_PAR_LCDL */
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600357#define GPIO_PAR_LCDL_LD11_UNMASK (0x3FFFFFFF)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600358#define GPIO_PAR_LCDL_LD11_LD11 (0xC0000000)
359#define GPIO_PAR_LCDL_LD11_LD7 (0x80000000)
360#define GPIO_PAR_LCDL_LD11_GPIO (0x00000000)
361
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600362#define GPIO_PAR_LCDL_LD10_UNMASK (0xCFFFFFFF)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600363#define GPIO_PAR_LCDL_LD10_LD10 (0x30000000)
364#define GPIO_PAR_LCDL_LD10_LD6 (0x20000000)
365#define GPIO_PAR_LCDL_LD10_GPIO (0x00000000)
366
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600367#define GPIO_PAR_LCDL_LD9_UNMASK (0xF3FFFFFF)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600368#define GPIO_PAR_LCDL_LD9_LD9 (0x0C000000)
369#define GPIO_PAR_LCDL_LD9_LD5 (0x08000000)
370#define GPIO_PAR_LCDL_LD9_GPIO (0x00000000)
371
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600372#define GPIO_PAR_LCDL_LD8_UNMASK (0xFCFFFFFF)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600373#define GPIO_PAR_LCDL_LD8_LD8 (0x03000000)
374#define GPIO_PAR_LCDL_LD8_LD4 (0x02000000)
375#define GPIO_PAR_LCDL_LD8_GPIO (0x00000000)
376
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600377#define GPIO_PAR_LCDL_LD7_UNMASK (0xFF3FFFFF)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600378#define GPIO_PAR_LCDL_LD7_LD7 (0x00C00000)
379#define GPIO_PAR_LCDL_LD7_PWM7 (0x00800000)
380#define GPIO_PAR_LCDL_LD7_GPIO (0x00000000)
381
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600382#define GPIO_PAR_LCDL_LD6_UNMASK (0xFFCFFFFF)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600383#define GPIO_PAR_LCDL_LD6_LD6 (0x00300000)
384#define GPIO_PAR_LCDL_LD6_PWM5 (0x00200000)
385#define GPIO_PAR_LCDL_LD6_GPIO (0x00000000)
386
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600387#define GPIO_PAR_LCDL_LD5_UNMASK (0xFFF3FFFF)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600388#define GPIO_PAR_LCDL_LD5_LD5 (0x000C0000)
389#define GPIO_PAR_LCDL_LD5_LD3 (0x00080000)
390#define GPIO_PAR_LCDL_LD5_GPIO (0x00000000)
391
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600392#define GPIO_PAR_LCDL_LD4_UNMASK (0xFFFCFFFF)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600393#define GPIO_PAR_LCDL_LD4_LD4 (0x00030000)
394#define GPIO_PAR_LCDL_LD4_LD2 (0x00020000)
395#define GPIO_PAR_LCDL_LD4_GPIO (0x00000000)
396
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600397#define GPIO_PAR_LCDL_LD3_UNMASK (0xFFFF3FFF)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600398#define GPIO_PAR_LCDL_LD3_LD3 (0x0000C000)
399#define GPIO_PAR_LCDL_LD3_LD1 (0x00008000)
400#define GPIO_PAR_LCDL_LD3_GPIO (0x00000000)
401
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600402#define GPIO_PAR_LCDL_LD2_UNMASK (0xFFFFCFFF)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600403#define GPIO_PAR_LCDL_LD2_LD2 (0x00003000)
404#define GPIO_PAR_LCDL_LD2_LD0 (0x00002000)
405#define GPIO_PAR_LCDL_LD2_GPIO (0x00000000)
406
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600407#define GPIO_PAR_LCDL_LD1_UNMASK (0xFFFFF3FF)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600408#define GPIO_PAR_LCDL_LD1_LD1 (0x00000C00)
409#define GPIO_PAR_LCDL_LD1_PWM3 (0x00000800)
410#define GPIO_PAR_LCDL_LD1_GPIO (0x00000000)
411
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600412#define GPIO_PAR_LCDL_LD0_UNMASK (0xFFFFFCFF)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600413#define GPIO_PAR_LCDL_LD0_LD0 (0x00000300)
414#define GPIO_PAR_LCDL_LD0_PWM1 (0x00000200)
415#define GPIO_PAR_LCDL_LD0_GPIO (0x00000000)
416
417/* Bit definitions and macros for MSCR_FB */
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600418#define GPIO_MSCR_FB_DUPPER_UNMASK (0xCF)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600419#define GPIO_MSCR_FB_DUPPER_25V_33V (0x30)
420#define GPIO_MSCR_FB_DUPPER_FULL_18V (0x20)
421#define GPIO_MSCR_FB_DUPPER_OD (0x10)
422#define GPIO_MSCR_FB_DUPPER_HALF_18V (0x00)
423
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600424#define GPIO_MSCR_FB_DLOWER_UNMASK (0xF3)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600425#define GPIO_MSCR_FB_DLOWER_25V_33V (0x0C)
426#define GPIO_MSCR_FB_DLOWER_FULL_18V (0x08)
427#define GPIO_MSCR_FB_DLOWER_OD (0x04)
428#define GPIO_MSCR_FB_DLOWER_HALF_18V (0x00)
429
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600430#define GPIO_MSCR_FB_ADDRCTL_UNMASK (0xFC)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600431#define GPIO_MSCR_FB_ADDRCTL_25V_33V (0x03)
432#define GPIO_MSCR_FB_ADDRCTL_FULL_18V (0x02)
433#define GPIO_MSCR_FB_ADDRCTL_OD (0x01)
434#define GPIO_MSCR_FB_ADDRCTL_HALF_18V (0x00)
435
436/* Bit definitions and macros for MSCR_SDRAM */
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600437#define GPIO_MSCR_SDRAM_SDCLKB_UNMASK (0xCF)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600438#define GPIO_MSCR_SDRAM_SDCLKB_25V_33V (0x30)
439#define GPIO_MSCR_SDRAM_SDCLKB_FULL_18V (0x20)
440#define GPIO_MSCR_SDRAM_SDCLKB_OD (0x10)
441#define GPIO_MSCR_SDRAM_SDCLKB_HALF_18V (0x00)
442
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600443#define GPIO_MSCR_SDRAM_SDCLK_UNMASK (0xF3)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600444#define GPIO_MSCR_SDRAM_SDCLK_25V_33V (0x0C)
445#define GPIO_MSCR_SDRAM_SDCLK_FULL_18V (0x08)
446#define GPIO_MSCR_SDRAM_SDCLK_OPD (0x04)
447#define GPIO_MSCR_SDRAM_SDCLK_HALF_18V (0x00)
448
TsiChung Liewd04c1ef2010-03-09 18:32:16 -0600449#define GPIO_MSCR_SDRAM_SDCTL_UNMASK (0xFC)
TsiChungLiewe2756f42008-01-14 17:47:23 -0600450#define GPIO_MSCR_SDRAM_SDCTL_25V_33V (0x03)
451#define GPIO_MSCR_SDRAM_SDCTL_FULL_18V (0x02)
452#define GPIO_MSCR_SDRAM_SDCTL_OPD (0x01)
453#define GPIO_MSCR_SDRAM_SDCTL_HALF_18V (0x00)
454
455/* Bit definitions and macros for Drive Strength Control */
456#define DSCR_LOAD_50PF (0x03)
457#define DSCR_LOAD_30PF (0x02)
458#define DSCR_LOAD_20PF (0x01)
459#define DSCR_LOAD_10PF (0x00)
460
461/*********************************************************************
462* SDRAM Controller (SDRAMC)
463*********************************************************************/
464
465/* Bit definitions and macros for SDMR */
466#define SDRAMC_SDMR_DDR2_AD(x) (((x)&0x00003FFF)) /* Address for DDR2 */
467#define SDRAMC_SDMR_CMD (0x00010000) /* Command */
468#define SDRAMC_SDMR_AD(x) (((x)&0x00000FFF)<<18) /* Address */
469#define SDRAMC_SDMR_BK(x) (((x)&0x00000003)<<30) /* Bank Address */
470#define SDRAMC_SDMR_BK_LMR (0x00000000)
471#define SDRAMC_SDMR_BK_LEMR (0x40000000)
472
473/* Bit definitions and macros for SDCR */
474#define SDRAMC_SDCR_DPD (0x00000001) /* Deep Power-Down Mode */
475#define SDRAMC_SDCR_IPALL (0x00000002) /* Initiate Precharge All */
476#define SDRAMC_SDCR_IREF (0x00000004) /* Initiate Refresh */
477#define SDRAMC_SDCR_DQS_OE(x) (((x)&0x00000003)<<10) /* DQS Output Enable */
478#define SDRAMC_SDCR_MEM_PS (0x00002000) /* Data Port Size */
479#define SDRAMC_SDCR_REF_CNT(x) (((x)&0x0000003F)<<16) /* Periodic Refresh Counter */
480#define SDRAMC_SDCR_OE_RULE (0x00400000) /* Drive Rule Selection */
481#define SDRAMC_SDCR_ADDR_MUX(x) (((x)&0x00000003)<<24) /* Internal Address Mux Select */
482#define SDRAMC_SDCR_DDR2_MODE (0x08000000) /* DDR2 Mode Select */
483#define SDRAMC_SDCR_REF_EN (0x10000000) /* Refresh Enable */
484#define SDRAMC_SDCR_DDR_MODE (0x20000000) /* DDR Mode Select */
485#define SDRAMC_SDCR_CKE (0x40000000) /* Clock Enable */
486#define SDRAMC_SDCR_MODE_EN (0x80000000) /* SDRAM Mode Register Programming Enable */
487#define SDRAMC_SDCR_DQS_OE_BOTH (0x00000C000)
488
489/* Bit definitions and macros for SDCFG1 */
490#define SDRAMC_SDCFG1_WT_LAT(x) (((x)&0x00000007)<<4) /* Write Latency */
491#define SDRAMC_SDCFG1_REF2ACT(x) (((x)&0x0000000F)<<8) /* Refresh to active delay */
492#define SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x00000007)<<12) /* Precharge to active delay */
493#define SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x00000007)<<16) /* Active to read/write delay */
494#define SDRAMC_SDCFG1_RD_LAT(x) (((x)&0x0000000F)<<20) /* Read CAS Latency */
495#define SDRAMC_SDCFG1_SWT2RWP(x) (((x)&0x00000007)<<24) /* Single write to read/write/precharge delay */
496#define SDRAMC_SDCFG1_SRD2RWP(x) (((x)&0x0000000F)<<28) /* Single read to read/write/precharge delay */
497
498/* Bit definitions and macros for SDCFG2 */
499#define SDRAMC_SDCFG2_BL(x) (((x)&0x0000000F)<<16) /* Burst Length */
500#define SDRAMC_SDCFG2_BRD2W(x) (((x)&0x0000000F)<<20) /* Burst read to write delay */
501#define SDRAMC_SDCFG2_BWT2RWP(x) (((x)&0x0000000F)<<24) /* Burst write to read/write/precharge delay */
502#define SDRAMC_SDCFG2_BRD2RP(x) (((x)&0x0000000F)<<28) /* Burst read to read/precharge delay */
503
504/* Bit definitions and macros for SDCS group */
505#define SDRAMC_SDCS_CSSZ(x) (((x)&0x0000001F)) /* Chip-Select Size */
506#define SDRAMC_SDCS_CSBA(x) (((x)&0x00000FFF)<<20) /* Chip-Select Base Address */
507#define SDRAMC_SDCS_BA(x) ((x)&0xFFF00000)
508#define SDRAMC_SDCS_CSSZ_DISABLE (0x00000000)
509#define SDRAMC_SDCS_CSSZ_1MBYTE (0x00000013)
510#define SDRAMC_SDCS_CSSZ_2MBYTE (0x00000014)
511#define SDRAMC_SDCS_CSSZ_4MBYTE (0x00000015)
512#define SDRAMC_SDCS_CSSZ_8MBYTE (0x00000016)
513#define SDRAMC_SDCS_CSSZ_16MBYTE (0x00000017)
514#define SDRAMC_SDCS_CSSZ_32MBYTE (0x00000018)
515#define SDRAMC_SDCS_CSSZ_64MBYTE (0x00000019)
516#define SDRAMC_SDCS_CSSZ_128MBYTE (0x0000001A)
517#define SDRAMC_SDCS_CSSZ_256MBYTE (0x0000001B)
518#define SDRAMC_SDCS_CSSZ_512MBYTE (0x0000001C)
519#define SDRAMC_SDCS_CSSZ_1GBYTE (0x0000001D)
520#define SDRAMC_SDCS_CSSZ_2GBYTE (0x0000001E)
521#define SDRAMC_SDCS_CSSZ_4GBYTE (0x0000001F)
522
523/*********************************************************************
524* Phase Locked Loop (PLL)
525*********************************************************************/
526
527/* Bit definitions and macros for PCR */
528#define PLL_PCR_OUTDIV1(x) (((x)&0x0000000F)) /* Output divider for CPU clock frequency */
529#define PLL_PCR_OUTDIV2(x) (((x)&0x0000000F)<<4) /* Output divider for bus/flexbus clock frequency */
530#define PLL_PCR_OUTDIV3(x) (((x)&0x0000000F)<<8) /* Output divider for SDRAM clock frequency */
531#define PLL_PCR_OUTDIV5(x) (((x)&0x0000000F)<<16) /* Output divider for USB clock frequency */
532#define PLL_PCR_PFDR(x) (((x)&0x000000FF)<<24) /* Feedback divider for VCO frequency */
533#define PLL_PCR_PFDR_MASK (0x000F0000)
534#define PLL_PCR_OUTDIV5_MASK (0x000F0000)
535#define PLL_PCR_OUTDIV3_MASK (0x00000F00)
536#define PLL_PCR_OUTDIV2_MASK (0x000000F0)
537#define PLL_PCR_OUTDIV1_MASK (0x0000000F)
538
539/* Bit definitions and macros for PSR */
540#define PLL_PSR_LOCKS (0x00000001) /* PLL lost lock - sticky */
541#define PLL_PSR_LOCK (0x00000002) /* PLL lock status */
542#define PLL_PSR_LOLIRQ (0x00000004) /* PLL loss-of-lock interrupt enable */
543#define PLL_PSR_LOLRE (0x00000008) /* PLL loss-of-lock reset enable */
544
545/********************************************************************/
546
547#endif /* __MCF5227X__ */