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Stelian Pop8e429b32008-05-08 18:52:23 +02001/*
2 * (C) Copyright 2007-2008
Stelian Popc9e798d2011-11-01 00:00:39 +01003 * Stelian Pop <stelian@popies.net>
Stelian Pop8e429b32008-05-08 18:52:23 +02004 * Lead Tech Design <www.leadtechdesign.com>
5 *
6 * Configuation settings for the AT91SAM9263EK board.
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Stelian Pop8e429b32008-05-08 18:52:23 +02009 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
Xu, Hongcd46b0f2011-06-10 21:31:26 +000014/*
15 * SoC must be defined first, before hardware.h is included.
16 * In this case SoC is defined in boards.cfg.
17 */
18#include <asm/hardware.h>
Stelian Pop8e429b32008-05-08 18:52:23 +020019
esw@bus-elektronik.de5e7d0912012-03-19 05:18:17 +000020#ifndef CONFIG_SYS_USE_BOOT_NORFLASH
Xu, Hongcd46b0f2011-06-10 21:31:26 +000021#define CONFIG_SYS_TEXT_BASE 0x21F00000
esw@bus-elektronik.de5e7d0912012-03-19 05:18:17 +000022#else
23#define CONFIG_SYS_TEXT_BASE 0x0000000
24#endif
Xu, Hongcd46b0f2011-06-10 21:31:26 +000025
26/* ARM asynchronous clock */
27#define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
28#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
Xu, Hongcd46b0f2011-06-10 21:31:26 +000029
30#define CONFIG_AT91SAM9263EK 1 /* It's an AT91SAM9263EK Board */
31
Jean-Christophe PLAGNIOL-VILLARDdc39ae92009-04-16 21:30:44 +020032#define CONFIG_ARCH_CPU_INIT
Stelian Pop8e429b32008-05-08 18:52:23 +020033
34#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
35#define CONFIG_SETUP_MEMORY_TAGS 1
36#define CONFIG_INITRD_TAG 1
37
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +020038#ifndef CONFIG_SYS_USE_BOOT_NORFLASH
Stelian Pop8e429b32008-05-08 18:52:23 +020039#define CONFIG_SKIP_LOWLEVEL_INIT
Xu, Hongcd46b0f2011-06-10 21:31:26 +000040#else
41#define CONFIG_SYS_USE_NORFLASH
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +020042#endif
Stelian Pop8e429b32008-05-08 18:52:23 +020043
Xu, Hongcd46b0f2011-06-10 21:31:26 +000044#define CONFIG_BOARD_EARLY_INIT_F
45
46#define CONFIG_DISPLAY_CPUINFO
47
Stelian Pop8e429b32008-05-08 18:52:23 +020048/*
49 * Hardware drivers
50 */
Xu, Hongcd46b0f2011-06-10 21:31:26 +000051#define CONFIG_ATMEL_LEGACY
52#define CONFIG_AT91_GPIO 1
53#define CONFIG_AT91_GPIO_PULLUP 1
54
55/* serial console */
56#define CONFIG_ATMEL_USART
57#define CONFIG_USART_BASE ATMEL_BASE_DBGU
58#define CONFIG_USART_ID ATMEL_ID_SYS
59#define CONFIG_BAUDRATE 115200
Stelian Pop8e429b32008-05-08 18:52:23 +020060
Stelian Pop56a24792008-05-08 14:52:31 +020061/* LCD */
62#define CONFIG_LCD 1
63#define LCD_BPP LCD_COLOR8
64#define CONFIG_LCD_LOGO 1
65#undef LCD_TEST_PATTERN
66#define CONFIG_LCD_INFO 1
67#define CONFIG_LCD_INFO_BELOW_LOGO 1
Xu, Hongcd46b0f2011-06-10 21:31:26 +000068#define CONFIG_SYS_WHITE_ON_BLACK 1
Stelian Pop56a24792008-05-08 14:52:31 +020069#define CONFIG_ATMEL_LCD 1
70#define CONFIG_ATMEL_LCD_BGR555 1
Xu, Hongcd46b0f2011-06-10 21:31:26 +000071#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
Stelian Pop56a24792008-05-08 14:52:31 +020072
Jean-Christophe PLAGNIOL-VILLARDa484b002009-03-21 21:08:00 +010073/* LED */
74#define CONFIG_AT91_LED
Xu, Hongcd46b0f2011-06-10 21:31:26 +000075#define CONFIG_RED_LED AT91_PIN_PB7 /* the power led */
76#define CONFIG_GREEN_LED AT91_PIN_PB8 /* the user1 led */
77#define CONFIG_YELLOW_LED AT91_PIN_PC29 /* the user2 led */
Jean-Christophe PLAGNIOL-VILLARDa484b002009-03-21 21:08:00 +010078
Stelian Pop8e429b32008-05-08 18:52:23 +020079
Stelian Pop8e429b32008-05-08 18:52:23 +020080/*
81 * BOOTP options
82 */
83#define CONFIG_BOOTP_BOOTFILESIZE 1
84#define CONFIG_BOOTP_BOOTPATH 1
85#define CONFIG_BOOTP_GATEWAY 1
86#define CONFIG_BOOTP_HOSTNAME 1
87
88/*
89 * Command line configuration.
90 */
Stelian Pop8e429b32008-05-08 18:52:23 +020091#define CONFIG_CMD_NAND 1
Stelian Pop8e429b32008-05-08 18:52:23 +020092
93/* SDRAM */
94#define CONFIG_NR_DRAM_BANKS 1
Xu, Hongcd46b0f2011-06-10 21:31:26 +000095#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
96#define CONFIG_SYS_SDRAM_SIZE 0x04000000
97
98#define CONFIG_SYS_INIT_SP_ADDR \
99 (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
Stelian Pop8e429b32008-05-08 18:52:23 +0200100
101/* DataFlash */
Jean-Christophe PLAGNIOL-VILLARD4758ebd2009-03-27 23:26:44 +0100102#define CONFIG_ATMEL_DATAFLASH_SPI
Stelian Pop8e429b32008-05-08 18:52:23 +0200103#define CONFIG_HAS_DATAFLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
105#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
Stelian Pop8e429b32008-05-08 18:52:23 +0200106#define AT91_SPI_CLK 15000000
107#define DATAFLASH_TCSS (0x1a << 16)
108#define DATAFLASH_TCHS (0x1 << 24)
109
Andreas Henriksson81724e02014-01-27 19:18:59 +0100110/* MMC */
111#ifdef CONFIG_CMD_MMC
112#define CONFIG_MMC
113#define CONFIG_GENERIC_MMC
114#define CONFIG_GENERIC_ATMEL_MCI
115#endif
116
Stelian Pop8e429b32008-05-08 18:52:23 +0200117/* NOR flash, if populated */
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200118#ifdef CONFIG_SYS_USE_NORFLASH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_FLASH_CFI 1
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200120#define CONFIG_FLASH_CFI_DRIVER 1
121#define PHYS_FLASH_1 0x10000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
123#define CONFIG_SYS_MAX_FLASH_SECT 256
124#define CONFIG_SYS_MAX_FLASH_BANKS 1
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200125
126#define CONFIG_SYS_MONITOR_SEC 1:0-3
127#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
128#define CONFIG_SYS_MONITOR_LEN (256 << 10)
129#define CONFIG_ENV_IS_IN_FLASH 1
esw@bus-elektronik.de5e7d0912012-03-19 05:18:17 +0000130#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007E0000)
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200131#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE)
132
133/* Address and size of Primary Environment Sector */
esw@bus-elektronik.de5e7d0912012-03-19 05:18:17 +0000134#define CONFIG_ENV_SIZE 0x10000
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200135
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200136#define CONFIG_EXTRA_ENV_SETTINGS \
Marek Vasut93ea89f2012-09-23 17:41:23 +0200137 "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200138 "update=" \
139 "protect off ${monitor_base} +${filesize};" \
140 "erase ${monitor_base} +${filesize};" \
Andreas Bießmann88461f12012-06-28 02:32:32 +0000141 "cp.b ${fileaddr} ${monitor_base} ${filesize};" \
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200142 "protect on ${monitor_base} +${filesize}\0"
143
144#ifndef CONFIG_SKIP_LOWLEVEL_INIT
145#define MASTER_PLL_MUL 171
146#define MASTER_PLL_DIV 14
Jens Scharsig1b34f002010-02-03 22:47:18 +0100147#define MASTER_PLL_OUT 3
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200148
149/* clocks */
150#define CONFIG_SYS_MOR_VAL \
Jens Scharsig1b34f002010-02-03 22:47:18 +0100151 (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
152#define CONFIG_SYS_PLLAR_VAL \
153 (AT91_PMC_PLLAR_29 | \
154 AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \
155 AT91_PMC_PLLXR_PLLCOUNT(63) | \
156 AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \
157 AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200158
159/* PCK/2 = MCK Master Clock from PLLA */
160#define CONFIG_SYS_MCKR1_VAL \
Jens Scharsig1b34f002010-02-03 22:47:18 +0100161 (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \
162 AT91_PMC_MCKR_MDIV_2)
163
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200164/* PCK/2 = MCK Master Clock from PLLA */
165#define CONFIG_SYS_MCKR2_VAL \
Jens Scharsig1b34f002010-02-03 22:47:18 +0100166 (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \
167 AT91_PMC_MCKR_MDIV_2)
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200168
169/* define PDC[31:16] as DATA[31:16] */
170#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
171/* no pull-up for D[31:16] */
172#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
173/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
Jens Scharsig1b34f002010-02-03 22:47:18 +0100174#define CONFIG_SYS_MATRIX_EBICSA_VAL \
175 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \
176 AT91_MATRIX_CSA_EBI_CS1A)
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200177
178/* SDRAM */
179/* SDRAMC_MR Mode register */
180#define CONFIG_SYS_SDRC_MR_VAL1 0
181/* SDRAMC_TR - Refresh Timer register */
182#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
183/* SDRAMC_CR - Configuration register*/
184#define CONFIG_SYS_SDRC_CR_VAL \
185 (AT91_SDRAMC_NC_9 | \
186 AT91_SDRAMC_NR_13 | \
187 AT91_SDRAMC_NB_4 | \
188 AT91_SDRAMC_CAS_3 | \
189 AT91_SDRAMC_DBW_32 | \
190 (1 << 8) | /* Write Recovery Delay */ \
191 (7 << 12) | /* Row Cycle Delay */ \
192 (2 << 16) | /* Row Precharge Delay */ \
193 (2 << 20) | /* Row to Column Delay */ \
194 (5 << 24) | /* Active to Precharge Delay */ \
195 (1 << 28)) /* Exit Self Refresh to Active Delay */
196
197/* Memory Device Register -> SDRAM */
198#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
199#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
200#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
201#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
202#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
203#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
204#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
205#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
206#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
207#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
208#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
209#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
210#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
211#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
212#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
213#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
214#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
215#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
216
217/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
Jens Scharsig1b34f002010-02-03 22:47:18 +0100218#define CONFIG_SYS_SMC0_SETUP0_VAL \
219 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
220 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
221#define CONFIG_SYS_SMC0_PULSE0_VAL \
222 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
223 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200224#define CONFIG_SYS_SMC0_CYCLE0_VAL \
Jens Scharsig1b34f002010-02-03 22:47:18 +0100225 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200226#define CONFIG_SYS_SMC0_MODE0_VAL \
Jens Scharsig1b34f002010-02-03 22:47:18 +0100227 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
228 AT91_SMC_MODE_DBW_16 | \
229 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200230
231/* user reset enable */
232#define CONFIG_SYS_RSTC_RMR_VAL \
233 (AT91_RSTC_KEY | \
Jens Scharsig1b34f002010-02-03 22:47:18 +0100234 AT91_RSTC_MR_URSTEN | \
235 AT91_RSTC_MR_ERSTL(15))
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200236
237/* Disable Watchdog */
238#define CONFIG_SYS_WDTC_WDMR_VAL \
Jens Scharsig1b34f002010-02-03 22:47:18 +0100239 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
240 AT91_WDT_MR_WDV(0xfff) | \
241 AT91_WDT_MR_WDDIS | \
242 AT91_WDT_MR_WDD(0xfff))
243
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200244#endif
245
246#else
247#define CONFIG_SYS_NO_FLASH 1
Stelian Pop8e429b32008-05-08 18:52:23 +0200248#endif
249
250/* NAND flash */
Jean-Christophe PLAGNIOL-VILLARD74c076d2009-03-22 10:22:34 +0100251#ifdef CONFIG_CMD_NAND
252#define CONFIG_NAND_ATMEL
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_MAX_NAND_DEVICE 1
Xu, Hongcd46b0f2011-06-10 21:31:26 +0000254#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_NAND_DBW_8 1
Jean-Christophe PLAGNIOL-VILLARD74c076d2009-03-22 10:22:34 +0100256/* our ALE is AD21 */
257#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
258/* our CLE is AD22 */
259#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
Xu, Hongcd46b0f2011-06-10 21:31:26 +0000260#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
261#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22
Jean-Christophe PLAGNIOL-VILLARD74c076d2009-03-22 10:22:34 +0100262#endif
Stelian Pop8e429b32008-05-08 18:52:23 +0200263
264/* Ethernet */
265#define CONFIG_MACB 1
266#define CONFIG_RMII 1
Stelian Pop8e429b32008-05-08 18:52:23 +0200267#define CONFIG_NET_RETRY_COUNT 20
268#define CONFIG_RESET_PHY_R 1
Heiko Schocher4535a242013-11-18 08:07:23 +0100269#define CONFIG_AT91_WANTS_COMMON_PHY
Stelian Pop8e429b32008-05-08 18:52:23 +0200270
271/* USB */
Jean-Christophe PLAGNIOL-VILLARD2b7178a2009-03-27 23:26:44 +0100272#define CONFIG_USB_ATMEL
Bo Shendcd2f1a2013-10-21 16:14:00 +0800273#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
Stelian Pop8e429b32008-05-08 18:52:23 +0200274#define CONFIG_USB_OHCI_NEW 1
Stelian Pop8e429b32008-05-08 18:52:23 +0200275#define CONFIG_DOS_PARTITION 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
277#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
278#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
279#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
Stelian Pop8e429b32008-05-08 18:52:23 +0200280#define CONFIG_USB_STORAGE 1
281
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
Stelian Pop8e429b32008-05-08 18:52:23 +0200283
Xu, Hongcd46b0f2011-06-10 21:31:26 +0000284#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_MEMTEST_END 0x23e00000
Stelian Pop8e429b32008-05-08 18:52:23 +0200286
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#ifdef CONFIG_SYS_USE_DATAFLASH
Stelian Pop8e429b32008-05-08 18:52:23 +0200288
289/* bootstrap + u-boot + env + linux in dataflash on CS0 */
Jean-Christophe PLAGNIOL-VILLARD057c8492008-09-10 22:47:58 +0200290#define CONFIG_ENV_IS_IN_DATAFLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200292#define CONFIG_ENV_OFFSET 0x4200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200294#define CONFIG_ENV_SIZE 0x4200
Alexandre Bellonie139cb32012-07-02 04:26:58 +0000295#define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm"
Stelian Pop8e429b32008-05-08 18:52:23 +0200296#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
297 "root=/dev/mtdblock0 " \
Albin Tonnerre918319c2009-07-22 18:30:03 +0200298 "mtdparts=atmel_nand:-(root) "\
Stelian Pop8e429b32008-05-08 18:52:23 +0200299 "rw rootfstype=jffs2"
300
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200301#elif CONFIG_SYS_USE_NANDFLASH
Stelian Pop8e429b32008-05-08 18:52:23 +0200302
303/* bootstrap + u-boot + env + linux in nandflash */
Xu, Hongcd46b0f2011-06-10 21:31:26 +0000304#define CONFIG_ENV_IS_IN_NAND 1
Bo Shen0c58cfa2013-02-20 00:16:25 +0000305#define CONFIG_ENV_OFFSET 0xc0000
306#define CONFIG_ENV_OFFSET_REDUND 0x100000
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200307#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
Bo Shen0c58cfa2013-02-20 00:16:25 +0000308#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm"
309#define CONFIG_BOOTARGS \
310 "console=ttyS0,115200 earlyprintk " \
311 "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \
312 "256k(env),256k(env_redundant),256k(spare)," \
313 "512k(dtb),6M(kernel)ro,-(rootfs) " \
314 "root=/dev/mtdblock7 rw rootfstype=jffs2"
Stelian Pop8e429b32008-05-08 18:52:23 +0200315#endif
316
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_CBSIZE 256
318#define CONFIG_SYS_MAXARGS 16
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_LONGHELP 1
Xu, Hongcd46b0f2011-06-10 21:31:26 +0000320#define CONFIG_CMDLINE_EDITING 1
Jean-Christophe PLAGNIOL-VILLARD03bab002009-03-30 16:51:40 +0200321#define CONFIG_AUTO_COMPLETE
Stelian Pop8e429b32008-05-08 18:52:23 +0200322
Stelian Pop8e429b32008-05-08 18:52:23 +0200323/*
324 * Size of malloc() pool
325 */
Xu, Hongcd46b0f2011-06-10 21:31:26 +0000326#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
Stelian Pop8e429b32008-05-08 18:52:23 +0200327
Stelian Pop8e429b32008-05-08 18:52:23 +0200328#endif