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Dirk Eibacha605ea72010-10-21 10:50:05 +02001/*
2 * (C) Copyright 2010
3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Dirk Eibacha605ea72010-10-21 10:50:05 +02006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11#define CONFIG_405EP 1 /* this is a PPC405 CPU */
Dirk Eibacha605ea72010-10-21 10:50:05 +020012#define CONFIG_IOCON 1 /* on a IoCon board */
13
14#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
15
16/*
17 * Include common defines/options for all AMCC eval boards
18 */
19#define CONFIG_HOSTNAME iocon
Dirk Eibachcccd4f42014-07-03 09:28:20 +020020#define CONFIG_IDENT_STRING " iocon 0.06"
Dirk Eibacha605ea72010-10-21 10:50:05 +020021#include "amcc-common.h"
22
Tom Rini57e5eca2016-01-19 13:01:59 -050023/* Reclaim some space. */
24#undef CONFIG_SYS_LONGHELP
25
Dirk Eibach6e9e6c32012-04-26 03:54:22 +000026#define CONFIG_BOARD_EARLY_INIT_F
27#define CONFIG_BOARD_EARLY_INIT_R
Dirk Eibacha605ea72010-10-21 10:50:05 +020028#define CONFIG_LAST_STAGE_INIT
29
30#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
31
32/*
33 * Configure PLL
34 */
35#define PLLMR0_DEFAULT PLLMR0_266_133_66
36#define PLLMR1_DEFAULT PLLMR1_266_133_66
37
Dirk Eibach996d88d2012-04-26 03:54:25 +000038#undef CONFIG_ZERO_BOOTDELAY_CHECK /* ignore keypress on bootdelay==0 */
Dirk Eibach996d88d2012-04-26 03:54:25 +000039
Dirk Eibacha605ea72010-10-21 10:50:05 +020040/* new uImage format support */
Dirk Eibach9a4f4792014-07-03 09:28:26 +020041#define CONFIG_FIT_DISABLE_SHA256
Dirk Eibacha605ea72010-10-21 10:50:05 +020042
43#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
44
45/*
46 * Default environment variables
47 */
48#define CONFIG_EXTRA_ENV_SETTINGS \
49 CONFIG_AMCC_DEF_ENV \
50 CONFIG_AMCC_DEF_ENV_POWERPC \
51 CONFIG_AMCC_DEF_ENV_NOR_UPD \
52 "kernel_addr=fc000000\0" \
53 "fdt_addr=fc1e0000\0" \
54 "ramdisk_addr=fc200000\0" \
55 ""
56
57#define CONFIG_PHY_ADDR 4 /* PHY address */
58#define CONFIG_HAS_ETH0
59#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
60
61/*
62 * Commands additional to the ones defined in amcc-common.h
63 */
Michal Simek7d2357c2014-06-17 00:36:14 +020064#define CONFIG_CMD_FPGAD
Dirk Eibacha605ea72010-10-21 10:50:05 +020065#undef CONFIG_CMD_EEPROM
Dirk Eibach4fb9b412014-07-03 09:28:25 +020066#undef CONFIG_CMD_IRQ
Dirk Eibacha605ea72010-10-21 10:50:05 +020067
68/*
69 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
70 */
71#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
72
73/* SDRAM timings used in datasheet */
74#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
75#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
76#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE period */
77#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
78#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
79
80/*
81 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
82 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
83 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD.
84 * The Linux BASE_BAUD define should match this configuration.
85 * baseBaud = cpuClock/(uartDivisor*16)
86 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
87 * set Linux BASE_BAUD to 403200.
88 */
89#define CONFIG_CONS_INDEX 1 /* Use UART0 */
90#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
91#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
92#define CONFIG_SYS_BASE_BAUD 691200
93
94/*
95 * I2C stuff
96 */
Heiko Schocherea818db2013-01-29 08:53:15 +010097#define CONFIG_SYS_I2C
Dirk Eibach880540d2013-04-25 02:40:01 +000098#define CONFIG_SYS_I2C_PPC4XX
99#define CONFIG_SYS_I2C_PPC4XX_CH0
100#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
101#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
Dirk Eibachb46226b2014-07-03 09:28:18 +0200102#define CONFIG_SYS_I2C_IHS
Dirk Eibacha605ea72010-10-21 10:50:05 +0200103
Dirk Eibache50e8962013-07-25 19:28:13 +0200104#define CONFIG_SYS_I2C_SPEED 400000
Dirk Eibachb46226b2014-07-03 09:28:18 +0200105#define CONFIG_SYS_SPD_BUS_NUM 4
Dirk Eibache50e8962013-07-25 19:28:13 +0200106
107#define CONFIG_PCA953X /* NXP PCA9554 */
108#define CONFIG_PCA9698 /* NXP PCA9698 */
109
Dirk Eibachb46226b2014-07-03 09:28:18 +0200110#define CONFIG_SYS_I2C_IHS_CH0
111#define CONFIG_SYS_I2C_IHS_SPEED_0 50000
112#define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F
113#define CONFIG_SYS_I2C_IHS_CH1
114#define CONFIG_SYS_I2C_IHS_SPEED_1 50000
115#define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F
116#define CONFIG_SYS_I2C_IHS_CH2
117#define CONFIG_SYS_I2C_IHS_SPEED_2 50000
118#define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F
119#define CONFIG_SYS_I2C_IHS_CH3
120#define CONFIG_SYS_I2C_IHS_SPEED_3 50000
121#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
122
Dirk Eibacha605ea72010-10-21 10:50:05 +0200123/*
124 * Software (bit-bang) I2C driver configuration
125 */
Dirk Eibache50e8962013-07-25 19:28:13 +0200126#define CONFIG_SYS_I2C_SOFT
127#define CONFIG_SYS_I2C_SOFT_SPEED 50000
128#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
129#define I2C_SOFT_DECLARATIONS2
130#define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
131#define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F
132#define I2C_SOFT_DECLARATIONS3
133#define CONFIG_SYS_I2C_SOFT_SPEED_3 50000
134#define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F
135#define I2C_SOFT_DECLARATIONS4
136#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
137#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
138
Dirk Eibachb46226b2014-07-03 09:28:18 +0200139#define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8}
140#define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8}
141#define CONFIG_SYS_DP501_I2C {0, 1, 2, 3}
Dirk Eibacha605ea72010-10-21 10:50:05 +0200142
143#ifndef __ASSEMBLY__
Dirk Eibache50e8962013-07-25 19:28:13 +0200144void fpga_gpio_set(unsigned int bus, int pin);
145void fpga_gpio_clear(unsigned int bus, int pin);
146int fpga_gpio_get(unsigned int bus, int pin);
Dirk Eibacha605ea72010-10-21 10:50:05 +0200147#endif
148
149#define I2C_ACTIVE { }
150#define I2C_TRISTATE { }
Dirk Eibache50e8962013-07-25 19:28:13 +0200151#define I2C_READ \
152 (fpga_gpio_get(I2C_ADAP_HWNR, 0x0040) ? 1 : 0)
153#define I2C_SDA(bit) \
154 do { \
155 if (bit) \
156 fpga_gpio_set(I2C_ADAP_HWNR, 0x0040); \
157 else \
158 fpga_gpio_clear(I2C_ADAP_HWNR, 0x0040); \
159 } while (0)
160#define I2C_SCL(bit) \
161 do { \
162 if (bit) \
163 fpga_gpio_set(I2C_ADAP_HWNR, 0x0020); \
164 else \
165 fpga_gpio_clear(I2C_ADAP_HWNR, 0x0020); \
166 } while (0)
Dirk Eibacha605ea72010-10-21 10:50:05 +0200167#define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */
168
169/*
170 * FLASH organization
171 */
172#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
173#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
174
175#define CONFIG_SYS_FLASH_BASE 0xFC000000
176#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
177
178#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
179#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sectors per chip*/
180
181#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase/ms */
182#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write/ms */
183
184#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buff'd writes */
Dirk Eibacha605ea72010-10-21 10:50:05 +0200185
186#define CONFIG_SYS_FLASH_EMPTY_INFO /* 'E' for empty sector on flinfo */
187#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* no warn upon unknown flash */
188
189#ifdef CONFIG_ENV_IS_IN_FLASH
190#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
191#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
192#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
193
194/* Address and size of Redundant Environment Sector */
195#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
196#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
197#endif
198
199/*
200 * PPC405 GPIO Configuration
201 */
202#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
203{ \
204/* GPIO Core 0 */ \
205{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast */ \
206{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
207{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
208{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
209{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
210{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO5 TS3 */ \
211{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
212{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
213{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
214{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
215{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
216{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
217{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
218{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
219{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 */ \
220{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 */ \
221{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 */ \
222{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 */ \
223{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 */ \
224{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 */ \
225{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 */ \
226{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 */ \
227{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 */ \
228{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 */ \
229{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD */ \
230{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
231{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
232{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
233{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx */ \
234{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
235{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 */ \
236{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 */ \
237} \
238}
239
240/*
241 * Definitions for initial stack pointer and data area (in data cache)
242 */
243/* use on chip memory (OCM) for temperary stack until sdram is tested */
244#define CONFIG_SYS_TEMP_STACK_OCM 1
245
246/* On Chip Memory location */
247#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
248#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
249#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* in SDRAM */
York Sunb39d1212016-04-06 13:22:10 -0700250#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
Dirk Eibacha605ea72010-10-21 10:50:05 +0200251
Dirk Eibacha605ea72010-10-21 10:50:05 +0200252#define CONFIG_SYS_GBL_DATA_OFFSET \
York Sunb39d1212016-04-06 13:22:10 -0700253 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Dirk Eibacha605ea72010-10-21 10:50:05 +0200254#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
255
256/*
257 * External Bus Controller (EBC) Setup
258 */
259
260/* Memory Bank 0 (NOR-FLASH) initialization */
261#define CONFIG_SYS_EBC_PB0AP 0xa382a880
262#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000
263
264/* Memory Bank 1 (NVRAM) initializatio */
265#define CONFIG_SYS_EBC_PB1AP 0x92015480
266#define CONFIG_SYS_EBC_PB1CR 0xFB858000
267
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100268/* Memory Bank 2 (FPGA0) initialization */
269#define CONFIG_SYS_FPGA0_BASE 0x7f100000
Dirk Eibacha605ea72010-10-21 10:50:05 +0200270#define CONFIG_SYS_EBC_PB2AP 0x02825080
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100271#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA0_BASE | 0x1a000)
Dirk Eibacha605ea72010-10-21 10:50:05 +0200272
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100273#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
274#define CONFIG_SYS_FPGA_DONE(k) 0x0010
275
276#define CONFIG_SYS_FPGA_COUNT 1
Dirk Eibacha605ea72010-10-21 10:50:05 +0200277
Dirk Eibache50e8962013-07-25 19:28:13 +0200278#define CONFIG_SYS_MCLINK_MAX 3
Dirk Eibachaba27ac2013-06-26 16:04:26 +0200279
Dirk Eibache50e8962013-07-25 19:28:13 +0200280#define CONFIG_SYS_FPGA_PTR \
281 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
Dirk Eibachaba27ac2013-06-26 16:04:26 +0200282
Dirk Eibacha605ea72010-10-21 10:50:05 +0200283/* Memory Bank 3 (Latches) initialization */
284#define CONFIG_SYS_LATCH_BASE 0x7f200000
285#define CONFIG_SYS_EBC_PB3AP 0x02025080
286#define CONFIG_SYS_EBC_PB3CR 0x7f21a000
287
288#define CONFIG_SYS_LATCH0_RESET 0xffef
289#define CONFIG_SYS_LATCH0_BOOT 0xffff
290#define CONFIG_SYS_LATCH1_RESET 0xffff
291#define CONFIG_SYS_LATCH1_BOOT 0xffff
292
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100293/*
294 * OSD Setup
295 */
296#define CONFIG_SYS_MPC92469AC
Dirk Eibache50e8962013-07-25 19:28:13 +0200297#define CONFIG_SYS_OSD_SCREENS 1
Dirk Eibachedfe9fe2014-07-03 09:28:17 +0200298#define CONFIG_SYS_DP501_DIFFERENTIAL
299#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
Dirk Eibache50e8962013-07-25 19:28:13 +0200300
301#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
302#define CONFIG_BITBANGMII_MULTI
Dirk Eibach2da0fc02011-01-21 09:31:21 +0100303
Dirk Eibacha605ea72010-10-21 10:50:05 +0200304#endif /* __CONFIG_H */