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Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +09001#ifndef __CONFIG_H
2#define __CONFIG_H
3
4#undef DEBUG
5
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +09006#define CONFIG_CPU_SH7751 1
7#define CONFIG_CPU_SH_TYPE_R 1
8#define CONFIG_R2DPLUS 1
9#define __LITTLE_ENDIAN__ 1
10
11/*
12 * Command line configuration.
13 */
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +090014#define CONFIG_CMD_PCI
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +090015#define CONFIG_CMD_IDE
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +090016#define CONFIG_DOS_PARTITION
Nobuhiro Iwamatsuc8d47272010-12-08 14:01:12 +090017#define CONFIG_CMD_SH_ZIMAGEBOOT
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +090018
19/* SCIF */
Jean-Christophe PLAGNIOL-VILLARD6c58a032008-08-13 01:40:38 +020020#define CONFIG_SCIF_CONSOLE 1
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +090021#define CONFIG_BAUDRATE 115200
22#define CONFIG_CONS_SCIF1 1
Helmut Raiger9660e442011-10-20 04:19:47 +000023#define CONFIG_BOARD_LATE_INIT
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +090024
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +090025#define CONFIG_BOOTARGS "console=ttySC0,115200"
26#define CONFIG_ENV_OVERWRITE 1
27
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +090028/* SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020029#define CONFIG_SYS_SDRAM_BASE (0x8C000000)
30#define CONFIG_SYS_SDRAM_SIZE (0x04000000)
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +090031
Nobuhiro Iwamatsu653f9852011-01-17 20:48:39 +090032#define CONFIG_SYS_TEXT_BASE 0x0FFC0000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020033#define CONFIG_SYS_LONGHELP
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020034#define CONFIG_SYS_CBSIZE 256
35#define CONFIG_SYS_PBSIZE 256
36#define CONFIG_SYS_MAXARGS 16
37#define CONFIG_SYS_BARGSIZE 512
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +090038
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020039#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
Wolfgang Denk14d0a022010-10-07 21:51:12 +020040#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +090041
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020042#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +090043/* Address of u-boot image in Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
45#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +090046/* Size of DRAM reserved for malloc() use */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +090049
50/*
Nobuhiro Iwamatsu873d97a2008-06-17 16:28:05 +090051 * NOR Flash ( Spantion S29GL256P )
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +090052 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +020054#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055#define CONFIG_SYS_FLASH_BASE (0xA0000000)
56#define CONFIG_SYS_MAX_FLASH_BANKS (1)
57#define CONFIG_SYS_MAX_FLASH_SECT 256
58#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +090059
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020060#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020061#define CONFIG_ENV_SECT_SIZE 0x40000
62#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +090064
65/*
66 * SuperH Clock setting
67 */
68#define CONFIG_SYS_CLK_FREQ 60000000
Nobuhiro Iwamatsu684a5012013-08-21 16:11:21 +090069#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
70#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Jean-Christophe PLAGNIOL-VILLARDbe45c632009-06-04 12:06:48 +020071#define CONFIG_SYS_TMU_CLK_DIV 4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +090073
74/*
75 * IDE support
76 */
77#define CONFIG_IDE_RESET 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_PIO_MODE 1
79#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
80#define CONFIG_SYS_IDE_MAXDEVICE 1
81#define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000
82#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
83#define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */
84#define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */
85#define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */
Albert Aribaudf2a37fc2010-08-08 05:17:05 +053086#define CONFIG_IDE_SWAP_IO
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +090087
88/*
89 * SuperH PCI Bridge Configration
90 */
91#define CONFIG_PCI
92#define CONFIG_SH4_PCI
93#define CONFIG_SH7751_PCI
94#define CONFIG_PCI_PNP
95#define CONFIG_PCI_SCAN_SHOW 1
96#define __io
97#define __mem_pci
98
99#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
100#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
101#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
102#define CONFIG_PCI_IO_BUS 0xFE240000 /* IO space base address */
103#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
104#define CONFIG_PCI_IO_SIZE 0x00040000 /* Size of IO window */
Yoshihiro Shimoda2db0e122009-02-25 16:04:26 +0900105#define CONFIG_PCI_SYS_BUS (CONFIG_SYS_SDRAM_BASE & 0x1fffffff)
106#define CONFIG_PCI_SYS_PHYS (CONFIG_SYS_SDRAM_BASE & 0x1fffffff)
107#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +0900108
Nobuhiro Iwamatsuf5e24662008-03-25 17:11:24 +0900109#endif /* __CONFIG_H */