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Sergei Poselenov5d108ac2008-04-30 11:42:50 +02001/*
2 * (C) Copyright 2008
3 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
4 *
5 * Wolfgang Denk <wd@denx.de>
6 * Copyright 2004 Freescale Semiconductor.
7 * (C) Copyright 2002,2003 Motorola,Inc.
8 * Xianghua Xiao <X.Xiao@motorola.com>
9 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020010 * SPDX-License-Identifier: GPL-2.0+
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020011 */
12
13/*
14 * Socrates
15 */
16
17#ifndef __CONFIG_H
18#define __CONFIG_H
19
20/* High Level Configuration Options */
21#define CONFIG_BOOKE 1 /* BOOKE */
22#define CONFIG_E500 1 /* BOOKE e500 family */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020023#define CONFIG_MPC8544 1
24#define CONFIG_SOCRATES 1
Anatolij Gustschin10865142015-08-13 23:58:01 +020025#define CONFIG_DISPLAY_BOARDINFO
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020026
Wolfgang Denk2ae18242010-10-06 09:05:45 +020027#define CONFIG_SYS_TEXT_BASE 0xfff80000
28
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020029#define CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +000030#define CONFIG_PCI_INDIRECT_BRIDGE
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020031
32#define CONFIG_TSEC_ENET /* tsec ethernet support */
33
34#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
Detlev Zundel3e79b582008-08-15 15:42:12 +020035#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020036
37#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
38
39/*
40 * Only possible on E500 Version 2 or newer cores.
41 */
42#define CONFIG_ENABLE_36BIT_PHYS 1
43
44/*
45 * sysclk for MPC85xx
46 *
47 * Two valid values are:
48 * 33000000
49 * 66000000
50 *
51 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
52 * is likely the desired value here, so that is now the default.
53 * The board, however, can run at 66MHz. In any event, this value
54 * must match the settings of some switches. Details can be found
55 * in the README.mpc85xxads.
56 */
57
58#ifndef CONFIG_SYS_CLK_FREQ
59#define CONFIG_SYS_CLK_FREQ 66666666
60#endif
61
62/*
63 * These can be toggled for performance analysis, otherwise use default.
64 */
65#define CONFIG_L2_CACHE /* toggle L2 cache */
66#define CONFIG_BTB /* toggle branch predition */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020067
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068#define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020069
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
71#define CONFIG_SYS_MEMTEST_START 0x00400000
72#define CONFIG_SYS_MEMTEST_END 0x00C00000
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020073
Timur Tabie46fedf2011-08-04 18:03:41 -050074#define CONFIG_SYS_CCSRBAR 0xE0000000
75#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020076
Kumar Galabe0bd822008-08-26 22:56:56 -050077/* DDR Setup */
York Sun5614e712013-09-30 09:22:09 -070078#define CONFIG_SYS_FSL_DDR2
Kumar Galabe0bd822008-08-26 22:56:56 -050079#undef CONFIG_FSL_DDR_INTERACTIVE
80#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
81#define CONFIG_DDR_SPD
82
83#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
84#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
85
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
87#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Galabe0bd822008-08-26 22:56:56 -050088#define CONFIG_VERY_BIG_RAM
89
90#define CONFIG_NUM_DDR_CONTROLLERS 1
91#define CONFIG_DIMM_SLOTS_PER_CTLR 1
92#define CONFIG_CHIP_SELECTS_PER_CTRL 2
93
94/* I2C addresses of SPD EEPROMs */
Anatolij Gustschin562788b2008-09-17 11:45:51 +020095#define SPD_EEPROM_ADDRESS 0x50 /* CTLR 0 DIMM 0 */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020096
97#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */
98
99/* Hardcoded values, to use instead of SPD */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
101#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
102#define CONFIG_SYS_DDR_TIMING_0 0x00260802
103#define CONFIG_SYS_DDR_TIMING_1 0x3935D322
104#define CONFIG_SYS_DDR_TIMING_2 0x14904CC8
105#define CONFIG_SYS_DDR_MODE 0x00480432
106#define CONFIG_SYS_DDR_INTERVAL 0x030C0100
107#define CONFIG_SYS_DDR_CONFIG_2 0x04400000
108#define CONFIG_SYS_DDR_CONFIG 0xC3008000
109#define CONFIG_SYS_DDR_CLK_CONTROL 0x03800000
110#define CONFIG_SYS_SDRAM_SIZE 256 /* in Megs */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200111
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200112/*
113 * Flash on the LocalBus
114 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200116
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_FLASH0 0xFE000000
118#define CONFIG_SYS_FLASH1 0xFC000000
119#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200120
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */
122#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200123
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_BR0_PRELIM 0xfe001001 /* port size 16bit */
125#define CONFIG_SYS_OR0_PRELIM 0xfe000030 /* 32MB Flash */
126#define CONFIG_SYS_BR1_PRELIM 0xfc001001 /* port size 16bit */
127#define CONFIG_SYS_OR1_PRELIM 0xfe000030 /* 32MB Flash */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200128
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200130#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200131
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
133#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
134#undef CONFIG_SYS_FLASH_CHECKSUM
135#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
136#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200137
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200138#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200139
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
141#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
142#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
143#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200144
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_INIT_RAM_LOCK 1
146#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200147#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200148
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200149#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200151
Detlev Zundel47106ce2010-04-14 11:32:20 +0200152#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384KiB for Mon */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc */
Detlev Zundel3e79b582008-08-15 15:42:12 +0200154
155/* FPGA and NAND */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_FPGA_BASE 0xc0000000
157#define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */
158#define CONFIG_SYS_HMI_BASE 0xc0010000
159#define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */
160#define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */
Detlev Zundel3e79b582008-08-15 15:42:12 +0200161
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70)
163#define CONFIG_SYS_MAX_NAND_DEVICE 1
Detlev Zundel3e79b582008-08-15 15:42:12 +0200164#define CONFIG_CMD_NAND
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200165
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200166/* LIME GDC */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_LIME_BASE 0xc8000000
168#define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */
169#define CONFIG_SYS_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */
170#define CONFIG_SYS_OR2_PRELIM 0xfc000000 /* 64 MB */
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200171
172#define CONFIG_VIDEO
173#define CONFIG_VIDEO_MB862xx
Anatolij Gustschin5d16ca82009-10-23 12:03:14 +0200174#define CONFIG_VIDEO_MB862xx_ACCEL
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200175#define CONFIG_CFB_CONSOLE
176#define CONFIG_VIDEO_LOGO
177#define CONFIG_VIDEO_BMP_LOGO
178#define CONFIG_CONSOLE_EXTRA_INFO
179#define VIDEO_FB_16BPP_PIXEL_SWAP
Wolfgang Grandegger229b6dc2009-10-23 12:03:15 +0200180#define VIDEO_FB_16BPP_WORD_SWAP
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200181#define CONFIG_VGA_AS_SINGLE_DEVICE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_CONSOLE_IS_IN_ENV
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200183#define CONFIG_VIDEO_SW_CURSOR
184#define CONFIG_SPLASH_SCREEN
185#define CONFIG_VIDEO_BMP_GZIP
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200187
Wolfgang Grandeggerc28d3bb2009-10-23 12:03:13 +0200188/* SDRAM Clock frequency, 100MHz (0x0000) or 133MHz (0x10000) */
189#define CONFIG_SYS_MB862xx_CCF 0x10000
190/* SDRAM parameter */
191#define CONFIG_SYS_MB862xx_MMR 0x4157BA63
192
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200193/* Serial Port */
194
195#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_NS16550_SERIAL
197#define CONFIG_SYS_NS16550_REG_SIZE 1
198#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200199
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
201#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200202
203#define CONFIG_BAUDRATE 115200
204
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_BAUDRATE_TABLE \
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200206 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
207
208#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Kim Phillips5be58f52010-07-14 19:47:18 -0500209#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200210
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200211/*
212 * I2C
213 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200214#define CONFIG_SYS_I2C
215#define CONFIG_SYS_I2C_FSL
216#define CONFIG_SYS_FSL_I2C_SPEED 102124
217#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
218#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
219#define CONFIG_SYS_FSL_I2C2_SPEED 102124
220#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
221#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Detlev Zundel3e79b582008-08-15 15:42:12 +0200222
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200223/* I2C RTC */
Sergei Poselenove18575d2008-05-07 15:10:49 +0200224#define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_I2C_RTC_ADDR 0x32 /* at address 0x32 */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200226
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200227/* I2C W83782G HW-Monitoring IC */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_I2C_W83782G_ADDR 0x28 /* W83782G address */
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200229
Sergei Poselenov2f7468a2008-05-27 10:36:07 +0200230/* I2C temp sensor */
231/* Socrates uses Maxim's DS75, which is compatible with LM75 */
232#define CONFIG_DTT_LM75 1
233#define CONFIG_DTT_SENSORS {4} /* Sensor addresses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_DTT_MAX_TEMP 125
235#define CONFIG_SYS_DTT_LOW_TEMP -55
236#define CONFIG_SYS_DTT_HYSTERESIS 3
237#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
Sergei Poselenov2f7468a2008-05-27 10:36:07 +0200238
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200239/*
240 * General PCI
241 * Memory space is mapped 1-1.
242 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200244
Sergei Poselenov5e1882d2008-05-27 13:47:00 +0200245/* PCI is clocked by the external source at 33 MHz */
246#define CONFIG_PCI_CLK_FREQ 33000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
248#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
249#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
250#define CONFIG_SYS_PCI1_IO_BASE 0xE2000000
251#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
252#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200253
254#if defined(CONFIG_PCI)
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200255#define CONFIG_PCI_PNP /* do pci plug-and-play */
Sergei Poselenovd39e6852008-06-06 15:42:39 +0200256#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200257#endif /* CONFIG_PCI */
258
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200259#define CONFIG_MII 1 /* MII PHY management */
260#define CONFIG_TSEC1 1
261#define CONFIG_TSEC1_NAME "TSEC0"
Sergei Poselenov2f845dc2008-05-08 17:46:23 +0200262#define CONFIG_TSEC3 1
263#define CONFIG_TSEC3_NAME "TSEC1"
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200264#undef CONFIG_MPC85XX_FEC
265
266#define TSEC1_PHY_ADDR 0
Sergei Poselenov2f845dc2008-05-08 17:46:23 +0200267#define TSEC3_PHY_ADDR 1
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200268
269#define TSEC1_PHYIDX 0
Sergei Poselenov2f845dc2008-05-08 17:46:23 +0200270#define TSEC3_PHYIDX 0
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200271#define TSEC1_FLAGS TSEC_GIGABIT
Sergei Poselenov2f845dc2008-05-08 17:46:23 +0200272#define TSEC3_FLAGS TSEC_GIGABIT
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200273
Sergei Poselenov2f845dc2008-05-08 17:46:23 +0200274/* Options are: TSEC[0,1] */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200275#define CONFIG_ETHPRIME "TSEC0"
276#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
277
Sergei Poselenove18575d2008-05-07 15:10:49 +0200278#define CONFIG_HAS_ETH0
279#define CONFIG_HAS_ETH1
280
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200281/*
282 * Environment
283 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200284#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200285#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200287#define CONFIG_ENV_SIZE 0x4000
288#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
289#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200290
291#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200293
294#define CONFIG_TIMESTAMP /* Print image info with ts */
295
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200296/*
297 * BOOTP options
298 */
299#define CONFIG_BOOTP_BOOTFILESIZE
300#define CONFIG_BOOTP_BOOTPATH
301#define CONFIG_BOOTP_GATEWAY
302#define CONFIG_BOOTP_HOSTNAME
303
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200304/*
305 * Command line configuration.
306 */
Detlev Zundel47106ce2010-04-14 11:32:20 +0200307#define CONFIG_CMD_BMP
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200308#define CONFIG_CMD_DATE
Sergei Poselenov2f7468a2008-05-27 10:36:07 +0200309#define CONFIG_CMD_DTT
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200310#undef CONFIG_CMD_EEPROM
Detlev Zundel3e79b582008-08-15 15:42:12 +0200311#define CONFIG_CMD_SDRAM
Becky Bruce199e2622010-06-17 11:37:25 -0500312#define CONFIG_CMD_REGINFO
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200313
314#if defined(CONFIG_PCI)
315 #define CONFIG_CMD_PCI
316#endif
317
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200318#undef CONFIG_WATCHDOG /* watchdog disabled */
319
320/*
321 * Miscellaneous configurable options
322 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_LONGHELP /* undef to save memory */
324#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200325
326#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200328#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200330#endif
331
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buf Size */
333#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
334#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200335
336/*
337 * For booting Linux, the board info and command line data
338 * have to be in the first 8 MB of memory, since this is
339 * the maximum mapped by the Linux kernel during initialization.
340 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200342
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200343#if defined(CONFIG_CMD_KGDB)
344#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200345#endif
346
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200347#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
348
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200349
350#define CONFIG_PREBOOT "echo;" \
Detlev Zundel3e79b582008-08-15 15:42:12 +0200351 "echo Welcome on the ABB Socrates Board;" \
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200352 "echo"
353
354#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
355
356#define CONFIG_EXTRA_ENV_SETTINGS \
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200357 "netdev=eth0\0" \
358 "consdev=ttyS0\0" \
Detlev Zundel3e79b582008-08-15 15:42:12 +0200359 "uboot_file=/home/tftp/syscon3/u-boot.bin\0" \
360 "bootfile=/home/tftp/syscon3/uImage\0" \
361 "fdt_file=/home/tftp/syscon3/socrates.dtb\0" \
362 "initrd_file=/home/tftp/syscon3/uinitrd.gz\0" \
363 "uboot_addr=FFFA0000\0" \
364 "kernel_addr=FE000000\0" \
365 "fdt_addr=FE1E0000\0" \
366 "ramdisk_addr=FE200000\0" \
367 "fdt_addr_r=B00000\0" \
368 "kernel_addr_r=200000\0" \
369 "ramdisk_addr_r=400000\0" \
370 "rootpath=/opt/eldk/ppc_85xxDP\0" \
371 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200372 "nfsargs=setenv bootargs root=/dev/nfs rw " \
373 "nfsroot=$serverip:$rootpath\0" \
Detlev Zundel3e79b582008-08-15 15:42:12 +0200374 "addcons=setenv bootargs $bootargs " \
375 "console=$consdev,$baudrate\0" \
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200376 "addip=setenv bootargs $bootargs " \
377 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
378 ":$hostname:$netdev:off panic=1\0" \
Detlev Zundel3e79b582008-08-15 15:42:12 +0200379 "boot_nor=run ramargs addcons;" \
Sergei Poselenove18575d2008-05-07 15:10:49 +0200380 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
Sergei Poselenove18575d2008-05-07 15:10:49 +0200381 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
382 "tftp ${fdt_addr_r} ${fdt_file}; " \
383 "run nfsargs addip addcons;" \
384 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
Detlev Zundel3e79b582008-08-15 15:42:12 +0200385 "update_uboot=tftp 100000 ${uboot_file};" \
386 "protect off fffa0000 ffffffff;" \
387 "era fffa0000 ffffffff;" \
388 "cp.b 100000 fffa0000 ${filesize};" \
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200389 "setenv filesize;saveenv\0" \
Detlev Zundel3e79b582008-08-15 15:42:12 +0200390 "update_kernel=tftp 100000 ${bootfile};" \
391 "era fe000000 fe1dffff;" \
392 "cp.b 100000 fe000000 ${filesize};" \
393 "setenv filesize;saveenv\0" \
394 "update_fdt=tftp 100000 ${fdt_file};" \
395 "era fe1e0000 fe1fffff;" \
396 "cp.b 100000 fe1e0000 ${filesize};" \
397 "setenv filesize;saveenv\0" \
398 "update_initrd=tftp 100000 ${initrd_file};" \
399 "era fe200000 fe9fffff;" \
400 "cp.b 100000 fe200000 ${filesize};" \
401 "setenv filesize;saveenv\0" \
402 "clean_data=era fea00000 fff5ffff\0" \
403 "usbargs=setenv bootargs root=/dev/sda1 rw\0" \
404 "load_usb=usb start;" \
405 "ext2load usb 0:1 ${kernel_addr_r} /boot/uImage\0" \
406 "boot_usb=run load_usb usbargs addcons;" \
407 "bootm ${kernel_addr_r} - ${fdt_addr};" \
408 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200409 ""
Detlev Zundel3e79b582008-08-15 15:42:12 +0200410#define CONFIG_BOOTCOMMAND "run boot_nor"
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200411
Sergei Poselenove18575d2008-05-07 15:10:49 +0200412/* pass open firmware flat tree */
Sergei Poselenove18575d2008-05-07 15:10:49 +0200413
Sergei Poselenov791e1db2008-05-27 11:49:13 +0200414/* USB support */
415#define CONFIG_USB_OHCI_NEW 1
416#define CONFIG_PCI_OHCI 1
417#define CONFIG_PCI_OHCI_DEVNO 3 /* Number in PCI list */
Yuri Tikhonove90fb6a2008-09-04 11:19:05 +0200418#define CONFIG_PCI_EHCI_DEVNO (CONFIG_PCI_OHCI_DEVNO / 2)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200419#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
420#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
421#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
Sergei Poselenov791e1db2008-05-27 11:49:13 +0200422#define CONFIG_DOS_PARTITION 1
423#define CONFIG_USB_STORAGE 1
424
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200425#endif /* __CONFIG_H */