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wdenk5b845b62002-08-21 21:57:24 +00001/*
wdenk5da627a2003-10-09 20:09:04 +00002 * (C) Copyright 2003
3 * Steven Scholz, imc Measurement & Control, steven.scholz@imc-berlin.de
4 *
wdenk5b845b62002-08-21 21:57:24 +00005 * (C) Copyright 2002
6 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 *
26 */
27
28/*
wdenk5b845b62002-08-21 21:57:24 +000029 * Altera FPGA support
30 */
31#include <common.h>
wdenk5da627a2003-10-09 20:09:04 +000032#include <ACEX1K.h>
eran liberty3c735e72008-03-27 00:50:49 +010033#include <stratixII.h>
wdenk5b845b62002-08-21 21:57:24 +000034
wdenk5da627a2003-10-09 20:09:04 +000035/* Define FPGA_DEBUG to get debug printf's */
36/* #define FPGA_DEBUG */
wdenk5b845b62002-08-21 21:57:24 +000037
38#ifdef FPGA_DEBUG
39#define PRINTF(fmt,args...) printf (fmt ,##args)
40#else
41#define PRINTF(fmt,args...)
42#endif
43
Matthias Fuchs01335022007-12-27 17:12:34 +010044#if defined(CONFIG_FPGA) && defined(CONFIG_FPGA_ALTERA)
wdenk5b845b62002-08-21 21:57:24 +000045
wdenk5da627a2003-10-09 20:09:04 +000046/* Local Static Functions */
eran liberty3c735e72008-03-27 00:50:49 +010047static int altera_validate (Altera_desc * desc, const char *fn);
wdenk5da627a2003-10-09 20:09:04 +000048
wdenk5b845b62002-08-21 21:57:24 +000049/* ------------------------------------------------------------------------- */
50int altera_load( Altera_desc *desc, void *buf, size_t bsize )
51{
wdenk5da627a2003-10-09 20:09:04 +000052 int ret_val = FPGA_FAIL; /* assume a failure */
53
Stefan Roese64cd52e2006-09-18 10:48:03 +020054 if (!altera_validate (desc, (char *)__FUNCTION__)) {
wdenk5da627a2003-10-09 20:09:04 +000055 printf ("%s: Invalid device descriptor\n", __FUNCTION__);
56 } else {
57 switch (desc->family) {
58 case Altera_ACEX1K:
Stefan Roesef0ff4692006-08-15 14:15:51 +020059 case Altera_CYC2:
Matthias Fuchs01335022007-12-27 17:12:34 +010060#if defined(CONFIG_FPGA_ACEX1K)
wdenk5da627a2003-10-09 20:09:04 +000061 PRINTF ("%s: Launching the ACEX1K Loader...\n",
62 __FUNCTION__);
63 ret_val = ACEX1K_load (desc, buf, bsize);
eran liberty3c735e72008-03-27 00:50:49 +010064#elif defined(CONFIG_FPGA_CYCLON2)
Stefan Roesef0ff4692006-08-15 14:15:51 +020065 PRINTF ("%s: Launching the CYCLON II Loader...\n",
66 __FUNCTION__);
67 ret_val = CYC2_load (desc, buf, bsize);
wdenk5da627a2003-10-09 20:09:04 +000068#else
69 printf ("%s: No support for ACEX1K devices.\n",
70 __FUNCTION__);
71#endif
72 break;
73
eran liberty3c735e72008-03-27 00:50:49 +010074#if defined(CONFIG_FPGA_STRATIX_II)
75 case Altera_StratixII:
76 PRINTF ("%s: Launching the Stratix II Loader...\n",
77 __FUNCTION__);
78 ret_val = StratixII_load (desc, buf, bsize);
79 break;
80#endif
wdenk5da627a2003-10-09 20:09:04 +000081 default:
82 printf ("%s: Unsupported family type, %d\n",
83 __FUNCTION__, desc->family);
84 }
85 }
86
87 return ret_val;
wdenk5b845b62002-08-21 21:57:24 +000088}
89
90int altera_dump( Altera_desc *desc, void *buf, size_t bsize )
91{
wdenk5da627a2003-10-09 20:09:04 +000092 int ret_val = FPGA_FAIL; /* assume a failure */
93
Stefan Roese64cd52e2006-09-18 10:48:03 +020094 if (!altera_validate (desc, (char *)__FUNCTION__)) {
wdenk5da627a2003-10-09 20:09:04 +000095 printf ("%s: Invalid device descriptor\n", __FUNCTION__);
96 } else {
97 switch (desc->family) {
98 case Altera_ACEX1K:
Matthias Fuchs01335022007-12-27 17:12:34 +010099#if defined(CONFIG_FPGA_ACEX)
wdenk5da627a2003-10-09 20:09:04 +0000100 PRINTF ("%s: Launching the ACEX1K Reader...\n",
101 __FUNCTION__);
102 ret_val = ACEX1K_dump (desc, buf, bsize);
103#else
104 printf ("%s: No support for ACEX1K devices.\n",
105 __FUNCTION__);
106#endif
107 break;
108
eran liberty3c735e72008-03-27 00:50:49 +0100109#if defined(CONFIG_FPGA_STRATIX_II)
110 case Altera_StratixII:
111 PRINTF ("%s: Launching the Stratix II Reader...\n",
112 __FUNCTION__);
113 ret_val = StratixII_dump (desc, buf, bsize);
114 break;
115#endif
wdenk5da627a2003-10-09 20:09:04 +0000116 default:
117 printf ("%s: Unsupported family type, %d\n",
118 __FUNCTION__, desc->family);
119 }
120 }
121
122 return ret_val;
wdenk5b845b62002-08-21 21:57:24 +0000123}
124
125int altera_info( Altera_desc *desc )
126{
wdenk5da627a2003-10-09 20:09:04 +0000127 int ret_val = FPGA_FAIL;
128
Stefan Roese64cd52e2006-09-18 10:48:03 +0200129 if (altera_validate (desc, (char *)__FUNCTION__)) {
wdenk5da627a2003-10-09 20:09:04 +0000130 printf ("Family: \t");
131 switch (desc->family) {
132 case Altera_ACEX1K:
133 printf ("ACEX1K\n");
134 break;
Stefan Roesef0ff4692006-08-15 14:15:51 +0200135 case Altera_CYC2:
136 printf ("CYCLON II\n");
137 break;
eran liberty3c735e72008-03-27 00:50:49 +0100138 case Altera_StratixII:
139 printf ("Stratix II\n");
140 break;
141 /* Add new family types here */
wdenk5da627a2003-10-09 20:09:04 +0000142 default:
143 printf ("Unknown family type, %d\n", desc->family);
144 }
145
146 printf ("Interface type:\t");
147 switch (desc->iface) {
148 case passive_serial:
149 printf ("Passive Serial (PS)\n");
150 break;
151 case passive_parallel_synchronous:
152 printf ("Passive Parallel Synchronous (PPS)\n");
153 break;
154 case passive_parallel_asynchronous:
155 printf ("Passive Parallel Asynchronous (PPA)\n");
156 break;
157 case passive_serial_asynchronous:
158 printf ("Passive Serial Asynchronous (PSA)\n");
159 break;
160 case altera_jtag_mode: /* Not used */
161 printf ("JTAG Mode\n");
162 break;
eran liberty3c735e72008-03-27 00:50:49 +0100163 case fast_passive_parallel:
164 printf ("Fast Passive Parallel (FPP)\n");
165 break;
166 case fast_passive_parallel_security:
167 printf
168 ("Fast Passive Parallel with Security (FPPS) \n");
169 break;
wdenk5da627a2003-10-09 20:09:04 +0000170 /* Add new interface types here */
171 default:
172 printf ("Unsupported interface type, %d\n", desc->iface);
173 }
174
175 printf ("Device Size: \t%d bytes\n"
176 "Cookie: \t0x%x (%d)\n",
177 desc->size, desc->cookie, desc->cookie);
178
179 if (desc->iface_fns) {
180 printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
181 switch (desc->family) {
182 case Altera_ACEX1K:
Stefan Roesef0ff4692006-08-15 14:15:51 +0200183 case Altera_CYC2:
Matthias Fuchs01335022007-12-27 17:12:34 +0100184#if defined(CONFIG_FPGA_ACEX1K)
wdenk5da627a2003-10-09 20:09:04 +0000185 ACEX1K_info (desc);
Matthias Fuchs01335022007-12-27 17:12:34 +0100186#elif defined(CONFIG_FPGA_CYCLON2)
Stefan Roesef0ff4692006-08-15 14:15:51 +0200187 CYC2_info (desc);
wdenk5da627a2003-10-09 20:09:04 +0000188#else
189 /* just in case */
190 printf ("%s: No support for ACEX1K devices.\n",
191 __FUNCTION__);
192#endif
193 break;
eran liberty3c735e72008-03-27 00:50:49 +0100194#if defined(CONFIG_FPGA_STRATIX_II)
195 case Altera_StratixII:
196 StratixII_info (desc);
197 break;
198#endif
wdenk5da627a2003-10-09 20:09:04 +0000199 /* Add new family types here */
200 default:
201 /* we don't need a message here - we give one up above */
wdenkb77fad32005-04-07 22:36:40 +0000202 break;
wdenk5da627a2003-10-09 20:09:04 +0000203 }
204 } else {
205 printf ("No Device Function Table.\n");
206 }
207
208 ret_val = FPGA_SUCCESS;
209 } else {
210 printf ("%s: Invalid device descriptor\n", __FUNCTION__);
211 }
212
213 return ret_val;
214}
215
216int altera_reloc( Altera_desc *desc, ulong reloc_offset)
217{
218 int ret_val = FPGA_FAIL; /* assume a failure */
219
Stefan Roese64cd52e2006-09-18 10:48:03 +0200220 if (!altera_validate (desc, (char *)__FUNCTION__)) {
wdenk5da627a2003-10-09 20:09:04 +0000221 printf ("%s: Invalid device descriptor\n", __FUNCTION__);
222 } else {
223 switch (desc->family) {
224 case Altera_ACEX1K:
Matthias Fuchs01335022007-12-27 17:12:34 +0100225#if defined(CONFIG_FPGA_ACEX1K)
wdenk5da627a2003-10-09 20:09:04 +0000226 ret_val = ACEX1K_reloc (desc, reloc_offset);
227#else
228 printf ("%s: No support for ACEX devices.\n",
229 __FUNCTION__);
230#endif
231 break;
eran liberty3c735e72008-03-27 00:50:49 +0100232#if defined(CONFIG_FPGA_STRATIX_II)
233 case Altera_StratixII:
234 ret_val = StratixII_reloc (desc, reloc_offset);
235 break;
236#endif
Stefan Roesef0ff4692006-08-15 14:15:51 +0200237 case Altera_CYC2:
Matthias Fuchs01335022007-12-27 17:12:34 +0100238#if defined(CONFIG_FPGA_CYCLON2)
Stefan Roesef0ff4692006-08-15 14:15:51 +0200239 ret_val = CYC2_reloc (desc, reloc_offset);
240#else
241 printf ("%s: No support for CYCLON II devices.\n",
242 __FUNCTION__);
243#endif
244 break;
wdenk5da627a2003-10-09 20:09:04 +0000245 /* Add new family types here */
246 default:
247 printf ("%s: Unsupported family type, %d\n",
248 __FUNCTION__, desc->family);
249 }
250 }
251
252 return ret_val;
wdenk5b845b62002-08-21 21:57:24 +0000253}
254
255/* ------------------------------------------------------------------------- */
256
eran liberty3c735e72008-03-27 00:50:49 +0100257static int altera_validate (Altera_desc * desc, const char *fn)
wdenk5da627a2003-10-09 20:09:04 +0000258{
259 int ret_val = FALSE;
260
261 if (desc) {
262 if ((desc->family > min_altera_type) &&
263 (desc->family < max_altera_type)) {
264 if ((desc->iface > min_altera_iface_type) &&
265 (desc->iface < max_altera_iface_type)) {
266 if (desc->size) {
267 ret_val = TRUE;
268 } else {
269 printf ("%s: NULL part size\n", fn);
270 }
271 } else {
272 printf ("%s: Invalid Interface type, %d\n",
273 fn, desc->iface);
274 }
275 } else {
276 printf ("%s: Invalid family type, %d\n", fn, desc->family);
277 }
278 } else {
279 printf ("%s: NULL descriptor!\n", fn);
280 }
281
282 return ret_val;
283}
wdenk5b845b62002-08-21 21:57:24 +0000284
285/* ------------------------------------------------------------------------- */
286
Matthias Fuchs01335022007-12-27 17:12:34 +0100287#endif /* CONFIG_FPGA & CONFIG_FPGA_ALTERA */