Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Stefan Roese | b0f80b9 | 2015-01-19 11:33:42 +0100 | [diff] [blame] | 2 | /* |
Stefan Roese | a5f8887 | 2016-01-07 14:09:09 +0100 | [diff] [blame] | 3 | * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de> |
Stefan Roese | b0f80b9 | 2015-01-19 11:33:42 +0100 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
Stefan Roese | 6451223 | 2015-11-25 07:37:00 +0100 | [diff] [blame] | 7 | #include <dm.h> |
| 8 | #include <debug_uart.h> |
| 9 | #include <fdtdec.h> |
Simon Glass | db41d65 | 2019-12-28 10:45:07 -0700 | [diff] [blame] | 10 | #include <hang.h> |
Simon Glass | 691d719 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 11 | #include <init.h> |
Stefan Roese | b0f80b9 | 2015-01-19 11:33:42 +0100 | [diff] [blame] | 12 | #include <spl.h> |
| 13 | #include <asm/io.h> |
| 14 | #include <asm/arch/cpu.h> |
| 15 | #include <asm/arch/soc.h> |
| 16 | |
Stefan Roese | a5f8887 | 2016-01-07 14:09:09 +0100 | [diff] [blame] | 17 | static u32 get_boot_device(void) |
| 18 | { |
| 19 | u32 val; |
| 20 | u32 boot_device; |
| 21 | |
Stefan Roese | f4db6c9 | 2016-01-07 14:12:04 +0100 | [diff] [blame] | 22 | /* |
| 23 | * First check, if UART boot-mode is active. This can only |
| 24 | * be done, via the bootrom error register. Here the |
| 25 | * MSB marks if the UART mode is active. |
| 26 | */ |
| 27 | val = readl(CONFIG_BOOTROM_ERR_REG); |
| 28 | boot_device = (val & BOOTROM_ERR_MODE_MASK) >> BOOTROM_ERR_MODE_OFFS; |
| 29 | debug("BOOTROM_REG=0x%08x boot_device=0x%x\n", val, boot_device); |
| 30 | if (boot_device == BOOTROM_ERR_MODE_UART) |
| 31 | return BOOT_DEVICE_UART; |
| 32 | |
Chris Packham | 2fd4284 | 2018-08-17 20:47:42 +1200 | [diff] [blame] | 33 | #ifdef CONFIG_ARMADA_38X |
| 34 | /* |
| 35 | * If the bootrom error code contains any other than zeros it's an |
| 36 | * error condition and the bootROM has fallen back to UART boot |
| 37 | */ |
| 38 | boot_device = (val & BOOTROM_ERR_CODE_MASK) >> BOOTROM_ERR_CODE_OFFS; |
| 39 | if (boot_device) |
| 40 | return BOOT_DEVICE_UART; |
| 41 | #endif |
| 42 | |
Stefan Roese | f4db6c9 | 2016-01-07 14:12:04 +0100 | [diff] [blame] | 43 | /* |
| 44 | * Now check the SAR register for the strapped boot-device |
| 45 | */ |
Stefan Roese | a5f8887 | 2016-01-07 14:09:09 +0100 | [diff] [blame] | 46 | val = readl(CONFIG_SAR_REG); /* SAR - Sample At Reset */ |
| 47 | boot_device = (val & BOOT_DEV_SEL_MASK) >> BOOT_DEV_SEL_OFFS; |
Stefan Roese | f4db6c9 | 2016-01-07 14:12:04 +0100 | [diff] [blame] | 48 | debug("SAR_REG=0x%08x boot_device=0x%x\n", val, boot_device); |
Stefan Roese | a5f8887 | 2016-01-07 14:09:09 +0100 | [diff] [blame] | 49 | switch (boot_device) { |
Sean Nyekjaer | 926c8b2 | 2017-11-24 14:01:47 +0100 | [diff] [blame] | 50 | #if defined(CONFIG_ARMADA_38X) |
| 51 | case BOOT_FROM_NAND: |
| 52 | return BOOT_DEVICE_NAND; |
| 53 | #endif |
Stefan Roese | a5f8887 | 2016-01-07 14:09:09 +0100 | [diff] [blame] | 54 | #ifdef CONFIG_SPL_MMC_SUPPORT |
| 55 | case BOOT_FROM_MMC: |
| 56 | case BOOT_FROM_MMC_ALT: |
| 57 | return BOOT_DEVICE_MMC1; |
| 58 | #endif |
| 59 | case BOOT_FROM_UART: |
Baruch Siach | f3a88e2 | 2017-09-24 15:50:17 +0300 | [diff] [blame] | 60 | #ifdef BOOT_FROM_UART_ALT |
| 61 | case BOOT_FROM_UART_ALT: |
| 62 | #endif |
Stefan Roese | a5f8887 | 2016-01-07 14:09:09 +0100 | [diff] [blame] | 63 | return BOOT_DEVICE_UART; |
Baruch Siach | 22c6545 | 2019-05-16 13:03:58 +0300 | [diff] [blame] | 64 | #ifdef BOOT_FROM_SATA |
| 65 | case BOOT_FROM_SATA: |
| 66 | case BOOT_FROM_SATA_ALT: |
| 67 | return BOOT_DEVICE_SATA; |
| 68 | #endif |
Stefan Roese | a5f8887 | 2016-01-07 14:09:09 +0100 | [diff] [blame] | 69 | case BOOT_FROM_SPI: |
| 70 | default: |
| 71 | return BOOT_DEVICE_SPI; |
| 72 | }; |
| 73 | } |
| 74 | |
Stefan Roese | b0f80b9 | 2015-01-19 11:33:42 +0100 | [diff] [blame] | 75 | u32 spl_boot_device(void) |
| 76 | { |
Stefan Roese | a5f8887 | 2016-01-07 14:09:09 +0100 | [diff] [blame] | 77 | return get_boot_device(); |
Stefan Roese | b0f80b9 | 2015-01-19 11:33:42 +0100 | [diff] [blame] | 78 | } |
| 79 | |
| 80 | void board_init_f(ulong dummy) |
| 81 | { |
Stefan Roese | 6451223 | 2015-11-25 07:37:00 +0100 | [diff] [blame] | 82 | int ret; |
| 83 | |
Stefan Roese | e3cccf9 | 2015-04-17 18:13:06 +0200 | [diff] [blame] | 84 | /* |
| 85 | * Pin muxing needs to be done before UART output, since |
| 86 | * on A38x the UART pins need some re-muxing for output |
| 87 | * to work. |
| 88 | */ |
| 89 | board_early_init_f(); |
| 90 | |
Stefan Roese | 6451223 | 2015-11-25 07:37:00 +0100 | [diff] [blame] | 91 | /* Example code showing how to enable the debug UART on MVEBU */ |
| 92 | #ifdef EARLY_UART |
| 93 | /* |
| 94 | * Debug UART can be used from here if required: |
| 95 | * |
| 96 | * debug_uart_init(); |
| 97 | * printch('a'); |
| 98 | * printhex8(0x1234); |
| 99 | * printascii("string"); |
| 100 | */ |
| 101 | #endif |
| 102 | |
Stefan Roese | f2100f6 | 2019-04-12 16:42:28 +0200 | [diff] [blame] | 103 | /* |
| 104 | * Use special translation offset for SPL. This needs to be |
| 105 | * configured *before* spl_init() is called as this function |
| 106 | * calls dm_init() which calls the bind functions of the |
| 107 | * device drivers. Here the base address needs to be configured |
| 108 | * (translated) correctly. |
| 109 | */ |
| 110 | gd->translation_offset = 0xd0000000 - 0xf1000000; |
| 111 | |
Stefan Roese | 6451223 | 2015-11-25 07:37:00 +0100 | [diff] [blame] | 112 | ret = spl_init(); |
| 113 | if (ret) { |
| 114 | debug("spl_init() failed: %d\n", ret); |
| 115 | hang(); |
| 116 | } |
| 117 | |
Stefan Roese | b0f80b9 | 2015-01-19 11:33:42 +0100 | [diff] [blame] | 118 | preloader_console_init(); |
| 119 | |
Stefan Roese | ade741b | 2015-07-15 15:36:52 +0200 | [diff] [blame] | 120 | timer_init(); |
| 121 | |
Stefan Roese | 09e89ab | 2016-02-10 07:23:00 +0100 | [diff] [blame] | 122 | /* Armada 375 does not support SerDes and DDR3 init yet */ |
| 123 | #if !defined(CONFIG_ARMADA_375) |
Stefan Roese | b0f80b9 | 2015-01-19 11:33:42 +0100 | [diff] [blame] | 124 | /* First init the serdes PHY's */ |
| 125 | serdes_phy_config(); |
| 126 | |
| 127 | /* Setup DDR */ |
| 128 | ddr3_init(); |
Stefan Roese | 09e89ab | 2016-02-10 07:23:00 +0100 | [diff] [blame] | 129 | #endif |
Stefan Roese | b0f80b9 | 2015-01-19 11:33:42 +0100 | [diff] [blame] | 130 | |
Baruch Siach | cc66ebd | 2019-07-10 18:23:04 +0300 | [diff] [blame] | 131 | /* Initialize Auto Voltage Scaling */ |
| 132 | mv_avs_init(); |
| 133 | |
Chris Packham | ad91fdf | 2020-02-26 19:53:50 +1300 | [diff] [blame] | 134 | /* Update read timing control for PCIe */ |
| 135 | mv_rtc_config(); |
| 136 | |
Stefan Roese | 944c7a3 | 2015-08-25 13:49:41 +0200 | [diff] [blame] | 137 | /* |
| 138 | * Return to the BootROM to continue the Marvell xmodem |
| 139 | * UART boot protocol. As initiated by the kwboot tool. |
| 140 | * |
| 141 | * This can only be done by the BootROM and not by the |
| 142 | * U-Boot SPL infrastructure, since the beginning of the |
| 143 | * image is already read and interpreted by the BootROM. |
| 144 | * SPL has no chance to receive this information. So we |
| 145 | * need to return to the BootROM to enable this xmodem |
| 146 | * UART download. |
Sean Nyekjaer | 926c8b2 | 2017-11-24 14:01:47 +0100 | [diff] [blame] | 147 | * |
| 148 | * If booting from NAND lets let the BootROM load the |
| 149 | * rest of the bootloader. |
Stefan Roese | 944c7a3 | 2015-08-25 13:49:41 +0200 | [diff] [blame] | 150 | */ |
Sean Nyekjaer | 926c8b2 | 2017-11-24 14:01:47 +0100 | [diff] [blame] | 151 | switch (get_boot_device()) { |
| 152 | case BOOT_DEVICE_UART: |
| 153 | #if defined(CONFIG_ARMADA_38X) |
| 154 | case BOOT_DEVICE_NAND: |
| 155 | #endif |
| 156 | return_to_bootrom(); |
| 157 | } |
Stefan Roese | b0f80b9 | 2015-01-19 11:33:42 +0100 | [diff] [blame] | 158 | } |