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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
maxims@google.com4dc038f2017-04-17 12:00:30 -07002/*
3 * Copyright (C) 2012-2020 ASPEED Technology Inc.
4 * Copyright 2016 IBM Corporation
5 * Copyright 2017 Google, Inc.
maxims@google.com4dc038f2017-04-17 12:00:30 -07006 */
7
8#include <common.h>
9#include <clk.h>
10#include <dm.h>
11#include <errno.h>
12#include <fdtdec.h>
13#include <i2c.h>
14#include <asm/io.h>
15#include <asm/arch/scu_ast2500.h>
Simon Glass61b29b82020-02-03 07:36:15 -070016#include <linux/err.h>
maxims@google.com4dc038f2017-04-17 12:00:30 -070017
18#include "ast_i2c.h"
19
20#define I2C_TIMEOUT_US 100000
21#define I2C_SLEEP_STEP_US 20
22
23#define HIGHSPEED_TTIMEOUT 3
24
maxims@google.com4dc038f2017-04-17 12:00:30 -070025/*
26 * Device private data
27 */
28struct ast_i2c_priv {
29 /* This device's clock */
30 struct clk clk;
31 /* Device registers */
32 struct ast_i2c_regs *regs;
33 /* I2C speed in Hz */
34 int speed;
35};
36
37/*
38 * Given desired divider ratio, return the value that needs to be set
39 * in Clock and AC Timing Control register
40 */
41static u32 get_clk_reg_val(ulong divider_ratio)
42{
43 ulong inc = 0, div;
44 ulong scl_low, scl_high, data;
45
46 for (div = 0; divider_ratio >= 16; div++) {
47 inc |= (divider_ratio & 1);
48 divider_ratio >>= 1;
49 }
50 divider_ratio += inc;
51 scl_low = (divider_ratio >> 1) - 1;
52 scl_high = divider_ratio - scl_low - 2;
53 data = I2CD_CACTC_BASE
54 | (scl_high << I2CD_TCKHIGH_SHIFT)
55 | (scl_low << I2CD_TCKLOW_SHIFT)
56 | (div << I2CD_BASE_DIV_SHIFT);
57
58 return data;
59}
60
61static void ast_i2c_clear_interrupts(struct udevice *dev)
62{
63 struct ast_i2c_priv *priv = dev_get_priv(dev);
64
65 writel(~0, &priv->regs->isr);
66}
67
68static void ast_i2c_init_bus(struct udevice *dev)
69{
70 struct ast_i2c_priv *priv = dev_get_priv(dev);
71
72 /* Reset device */
73 writel(0, &priv->regs->fcr);
74 /* Enable Master Mode. Assuming single-master */
75 writel(I2CD_MASTER_EN
76 | I2CD_M_SDA_LOCK_EN
77 | I2CD_MULTI_MASTER_DIS | I2CD_M_SCL_DRIVE_EN,
78 &priv->regs->fcr);
79 /* Enable Interrupts */
80 writel(I2CD_INTR_TX_ACK
81 | I2CD_INTR_TX_NAK
82 | I2CD_INTR_RX_DONE
83 | I2CD_INTR_BUS_RECOVER_DONE
84 | I2CD_INTR_NORMAL_STOP
85 | I2CD_INTR_ABNORMAL, &priv->regs->icr);
86}
87
88static int ast_i2c_ofdata_to_platdata(struct udevice *dev)
89{
90 struct ast_i2c_priv *priv = dev_get_priv(dev);
91 int ret;
92
Simon Glassa821c4a2017-05-17 17:18:05 -060093 priv->regs = devfdt_get_addr_ptr(dev);
maxims@google.com4dc038f2017-04-17 12:00:30 -070094 if (IS_ERR(priv->regs))
95 return PTR_ERR(priv->regs);
96
97 ret = clk_get_by_index(dev, 0, &priv->clk);
98 if (ret < 0) {
99 debug("%s: Can't get clock for %s: %d\n", __func__, dev->name,
100 ret);
101 return ret;
102 }
103
104 return 0;
105}
106
107static int ast_i2c_probe(struct udevice *dev)
108{
109 struct ast2500_scu *scu;
110
111 debug("Enabling I2C%u\n", dev->seq);
112
113 /*
114 * Get all I2C devices out of Reset.
115 * Only needs to be done once, but doing it for every
116 * device does not hurt.
117 */
118 scu = ast_get_scu();
119 ast_scu_unlock(scu);
120 clrbits_le32(&scu->sysreset_ctrl1, SCU_SYSRESET_I2C);
121 ast_scu_lock(scu);
122
123 ast_i2c_init_bus(dev);
124
125 return 0;
126}
127
128static int ast_i2c_wait_isr(struct udevice *dev, u32 flag)
129{
130 struct ast_i2c_priv *priv = dev_get_priv(dev);
131 int timeout = I2C_TIMEOUT_US;
132
133 while (!(readl(&priv->regs->isr) & flag) && timeout > 0) {
134 udelay(I2C_SLEEP_STEP_US);
135 timeout -= I2C_SLEEP_STEP_US;
136 }
137
138 ast_i2c_clear_interrupts(dev);
139 if (timeout <= 0)
140 return -ETIMEDOUT;
141
142 return 0;
143}
144
145static int ast_i2c_send_stop(struct udevice *dev)
146{
147 struct ast_i2c_priv *priv = dev_get_priv(dev);
148
149 writel(I2CD_M_STOP_CMD, &priv->regs->csr);
150
151 return ast_i2c_wait_isr(dev, I2CD_INTR_NORMAL_STOP);
152}
153
154static int ast_i2c_wait_tx(struct udevice *dev)
155{
156 struct ast_i2c_priv *priv = dev_get_priv(dev);
157 int timeout = I2C_TIMEOUT_US;
158 u32 flag = I2CD_INTR_TX_ACK | I2CD_INTR_TX_NAK;
159 u32 status = readl(&priv->regs->isr) & flag;
160 int ret = 0;
161
162 while (!status && timeout > 0) {
163 status = readl(&priv->regs->isr) & flag;
164 udelay(I2C_SLEEP_STEP_US);
165 timeout -= I2C_SLEEP_STEP_US;
166 }
167
168 if (status == I2CD_INTR_TX_NAK)
169 ret = -EREMOTEIO;
170
171 if (timeout <= 0)
172 ret = -ETIMEDOUT;
173
174 ast_i2c_clear_interrupts(dev);
175
176 return ret;
177}
178
179static int ast_i2c_start_txn(struct udevice *dev, uint devaddr)
180{
181 struct ast_i2c_priv *priv = dev_get_priv(dev);
182
183 /* Start and Send Device Address */
184 writel(devaddr, &priv->regs->trbbr);
185 writel(I2CD_M_START_CMD | I2CD_M_TX_CMD, &priv->regs->csr);
186
187 return ast_i2c_wait_tx(dev);
188}
189
190static int ast_i2c_read_data(struct udevice *dev, u8 chip_addr, u8 *buffer,
191 size_t len, bool send_stop)
192{
193 struct ast_i2c_priv *priv = dev_get_priv(dev);
194 u32 i2c_cmd = I2CD_M_RX_CMD;
195 int ret;
196
197 ret = ast_i2c_start_txn(dev, (chip_addr << 1) | I2C_M_RD);
198 if (ret < 0)
199 return ret;
200
201 for (; len > 0; len--, buffer++) {
202 if (len == 1)
203 i2c_cmd |= I2CD_M_S_RX_CMD_LAST;
204 writel(i2c_cmd, &priv->regs->csr);
205 ret = ast_i2c_wait_isr(dev, I2CD_INTR_RX_DONE);
206 if (ret < 0)
207 return ret;
208 *buffer = (readl(&priv->regs->trbbr) & I2CD_RX_DATA_MASK)
209 >> I2CD_RX_DATA_SHIFT;
210 }
211 ast_i2c_clear_interrupts(dev);
212
213 if (send_stop)
214 return ast_i2c_send_stop(dev);
215
216 return 0;
217}
218
219static int ast_i2c_write_data(struct udevice *dev, u8 chip_addr, u8
220 *buffer, size_t len, bool send_stop)
221{
222 struct ast_i2c_priv *priv = dev_get_priv(dev);
223 int ret;
224
225 ret = ast_i2c_start_txn(dev, (chip_addr << 1));
226 if (ret < 0)
227 return ret;
228
229 for (; len > 0; len--, buffer++) {
230 writel(*buffer, &priv->regs->trbbr);
231 writel(I2CD_M_TX_CMD, &priv->regs->csr);
232 ret = ast_i2c_wait_tx(dev);
233 if (ret < 0)
234 return ret;
235 }
236
237 if (send_stop)
238 return ast_i2c_send_stop(dev);
239
240 return 0;
241}
242
243static int ast_i2c_deblock(struct udevice *dev)
244{
245 struct ast_i2c_priv *priv = dev_get_priv(dev);
246 struct ast_i2c_regs *regs = priv->regs;
247 u32 csr = readl(&regs->csr);
248 bool sda_high = csr & I2CD_SDA_LINE_STS;
249 bool scl_high = csr & I2CD_SCL_LINE_STS;
250 int ret = 0;
251
252 if (sda_high && scl_high) {
253 /* Bus is idle, no deblocking needed. */
254 return 0;
255 } else if (sda_high) {
256 /* Send stop command */
257 debug("Unterminated TXN in (%x), sending stop\n", csr);
258 ret = ast_i2c_send_stop(dev);
259 } else if (scl_high) {
260 /* Possibly stuck slave */
261 debug("Bus stuck (%x), attempting recovery\n", csr);
262 writel(I2CD_BUS_RECOVER_CMD, &regs->csr);
263 ret = ast_i2c_wait_isr(dev, I2CD_INTR_BUS_RECOVER_DONE);
264 } else {
265 /* Just try to reinit the device. */
266 ast_i2c_init_bus(dev);
267 }
268
269 return ret;
270}
271
272static int ast_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
273{
274 int ret;
275
276 ret = ast_i2c_deblock(dev);
277 if (ret < 0)
278 return ret;
279
280 debug("i2c_xfer: %d messages\n", nmsgs);
281 for (; nmsgs > 0; nmsgs--, msg++) {
282 if (msg->flags & I2C_M_RD) {
283 debug("i2c_read: chip=0x%x, len=0x%x, flags=0x%x\n",
284 msg->addr, msg->len, msg->flags);
285 ret = ast_i2c_read_data(dev, msg->addr, msg->buf,
286 msg->len, (nmsgs == 1));
287 } else {
288 debug("i2c_write: chip=0x%x, len=0x%x, flags=0x%x\n",
289 msg->addr, msg->len, msg->flags);
290 ret = ast_i2c_write_data(dev, msg->addr, msg->buf,
291 msg->len, (nmsgs == 1));
292 }
293 if (ret) {
294 debug("%s: error (%d)\n", __func__, ret);
295 return -EREMOTEIO;
296 }
297 }
298
299 return 0;
300}
301
302static int ast_i2c_set_speed(struct udevice *dev, unsigned int speed)
303{
304 struct ast_i2c_priv *priv = dev_get_priv(dev);
305 struct ast_i2c_regs *regs = priv->regs;
306 ulong i2c_rate, divider;
307
308 debug("Setting speed for I2C%d to <%u>\n", dev->seq, speed);
309 if (!speed) {
310 debug("No valid speed specified\n");
311 return -EINVAL;
312 }
313
314 i2c_rate = clk_get_rate(&priv->clk);
315 divider = i2c_rate / speed;
316
317 priv->speed = speed;
Simon Glass642400c2020-01-23 11:48:17 -0700318 if (speed > I2C_SPEED_FAST_RATE) {
maxims@google.com4dc038f2017-04-17 12:00:30 -0700319 debug("Enable High Speed\n");
320 setbits_le32(&regs->fcr, I2CD_M_HIGH_SPEED_EN
321 | I2CD_M_SDA_DRIVE_1T_EN
322 | I2CD_SDA_DRIVE_1T_EN);
323 writel(HIGHSPEED_TTIMEOUT, &regs->cactcr2);
324 } else {
325 debug("Enabling Normal Speed\n");
326 writel(I2CD_NO_TIMEOUT_CTRL, &regs->cactcr2);
327 }
328
329 writel(get_clk_reg_val(divider), &regs->cactcr1);
330 ast_i2c_clear_interrupts(dev);
331
332 return 0;
333}
334
335static const struct dm_i2c_ops ast_i2c_ops = {
336 .xfer = ast_i2c_xfer,
337 .set_bus_speed = ast_i2c_set_speed,
338 .deblock = ast_i2c_deblock,
339};
340
341static const struct udevice_id ast_i2c_ids[] = {
342 { .compatible = "aspeed,ast2400-i2c-bus" },
343 { .compatible = "aspeed,ast2500-i2c-bus" },
344 { },
345};
346
347U_BOOT_DRIVER(ast_i2c) = {
348 .name = "ast_i2c",
349 .id = UCLASS_I2C,
350 .of_match = ast_i2c_ids,
351 .probe = ast_i2c_probe,
352 .ofdata_to_platdata = ast_i2c_ofdata_to_platdata,
353 .priv_auto_alloc_size = sizeof(struct ast_i2c_priv),
354 .ops = &ast_i2c_ops,
355};