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Michal Simek76316a32007-03-11 13:42:58 +01001/*
2 * (C) Copyright 2007 Michal Simek
3 *
4 * Michal SIMEK <monstr@monstr.eu>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/* This is a board specific file. It's OK to include board specific
26 * header files */
27
28#include <common.h>
Michal Simek342cd092007-03-30 22:52:09 +020029#include <config.h>
Michal Simekd69f8f42010-08-02 14:42:09 +020030#include <netdev.h>
Michal Simek19bf1fb2007-05-07 19:33:51 +020031#include <asm/microblaze_intc.h>
32#include <asm/asm.h>
Michal Simek76316a32007-03-11 13:42:58 +010033
Mike Frysinger882b7d72010-10-20 03:41:17 -040034int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
Michal Simek76316a32007-03-11 13:42:58 +010035{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020036#ifdef CONFIG_SYS_GPIO_0
37 *((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) =
38 ++(*((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)));
Michal Simek76316a32007-03-11 13:42:58 +010039#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040#ifdef CONFIG_SYS_RESET_ADDRESS
Michal Simek76316a32007-03-11 13:42:58 +010041 puts ("Reseting board\n");
42 asm ("bra r0");
43#endif
Mike Frysinger882b7d72010-10-20 03:41:17 -040044 return 0;
Michal Simek76316a32007-03-11 13:42:58 +010045}
46
47int gpio_init (void)
48{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049#ifdef CONFIG_SYS_GPIO_0
50 *((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) = 0xFFFFFFFF;
Michal Simek76316a32007-03-11 13:42:58 +010051#endif
52 return 0;
53}
Michal Simek19bf1fb2007-05-07 19:33:51 +020054
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020055#ifdef CONFIG_SYS_FSL_2
Michal Simek19bf1fb2007-05-07 19:33:51 +020056void fsl_isr2 (void *arg) {
57 volatile int num;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020058 *((unsigned int *)(CONFIG_SYS_GPIO_0_ADDR + 0x4)) =
59 ++(*((unsigned int *)(CONFIG_SYS_GPIO_0_ADDR + 0x4)));
Michal Simek19bf1fb2007-05-07 19:33:51 +020060 GET (num, 2);
61 NGET (num, 2);
62 puts("*");
63}
64
Michal Simekb2664092010-04-16 11:43:43 +020065int fsl_init2 (void) {
Michal Simek19bf1fb2007-05-07 19:33:51 +020066 puts("fsl_init2\n");
Michal Simekb2664092010-04-16 11:43:43 +020067 install_interrupt_handler (FSL_INTR_2, fsl_isr2, NULL);
68 return 0;
Michal Simek19bf1fb2007-05-07 19:33:51 +020069}
70#endif
Michal Simekd69f8f42010-08-02 14:42:09 +020071
72int board_eth_init(bd_t *bis)
73{
Michal Simekc1044a12011-10-12 23:23:22 +000074 int ret = 0;
Michal Simeke6341382011-08-31 11:51:50 +020075
76#ifdef CONFIG_XILINX_AXIEMAC
77 ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
78 XILINX_AXIDMA_BASEADDR);
79#endif
80
Michal Simekd69f8f42010-08-02 14:42:09 +020081#ifdef CONFIG_XILINX_EMACLITE
Michal Simekc1044a12011-10-12 23:23:22 +000082 u32 txpp = 0;
83 u32 rxpp = 0;
84# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
85 txpp = 1;
86# endif
87# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
88 rxpp = 1;
89# endif
90 ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
91 txpp, rxpp);
Michal Simekd69f8f42010-08-02 14:42:09 +020092#endif
Stephan Linz3ceecef2012-02-25 00:48:34 +000093
94#ifdef CONFIG_XILINX_LL_TEMAC
95# ifdef XILINX_LLTEMAC_BASEADDR
96# ifdef XILINX_LLTEMAC_FIFO_BASEADDR
97 ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR,
98 XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR);
99# elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR
100# if XILINX_LLTEMAC_SDMA_USE_DCR == 1
101 ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR,
102 XILINX_LL_TEMAC_M_SDMA_DCR,
103 XILINX_LLTEMAC_SDMA_CTRL_BASEADDR);
104# else
105 ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR,
106 XILINX_LL_TEMAC_M_SDMA_PLB,
107 XILINX_LLTEMAC_SDMA_CTRL_BASEADDR);
108# endif
109# endif
110# endif
111# ifdef XILINX_LLTEMAC_BASEADDR1
112# ifdef XILINX_LLTEMAC_FIFO_BASEADDR1
113 ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1,
114 XILINX_LL_TEMAC_M_FIFO, XILINX_LLTEMAC_FIFO_BASEADDR1);
115# elif XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1
116# if XILINX_LLTEMAC_SDMA_USE_DCR == 1
117 ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1,
118 XILINX_LL_TEMAC_M_SDMA_DCR,
119 XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1);
120# else
121 ret |= xilinx_ll_temac_eth_init(bis, XILINX_LLTEMAC_BASEADDR1,
122 XILINX_LL_TEMAC_M_SDMA_PLB,
123 XILINX_LLTEMAC_SDMA_CTRL_BASEADDR1);
124# endif
125# endif
126# endif
127#endif
128
Michal Simekc1044a12011-10-12 23:23:22 +0000129 return ret;
Michal Simekd69f8f42010-08-02 14:42:09 +0200130}