blob: 6e8a313db35bcbde943140dc4c3850031c52000f [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Stefan Roesef0ff4692006-08-15 14:15:51 +02002/*
3 * (C) Copyright 2006
4 * Heiko Schocher, hs@denx.de
5 * Based on ACE1XK.c
Stefan Roesef0ff4692006-08-15 14:15:51 +02006 */
7
Alexander Dahl29e58112022-10-07 14:19:59 +02008#define LOG_CATEGORY UCLASS_FPGA
9
Stefan Roesef0ff4692006-08-15 14:15:51 +020010#include <common.h> /* core U-Boot definitions */
Alexander Dahl29e58112022-10-07 14:19:59 +020011#include <log.h>
Stefan Roesef0ff4692006-08-15 14:15:51 +020012#include <altera.h>
13#include <ACEX1K.h> /* ACEX device family */
Simon Glassc05ed002020-05-10 11:40:11 -060014#include <linux/delay.h>
Stefan Roesef0ff4692006-08-15 14:15:51 +020015
Stefan Roesef0ff4692006-08-15 14:15:51 +020016/* Note: The assumption is that we cannot possibly run fast enough to
17 * overrun the device (the Slave Parallel mode can free run at 50MHz).
Tom Rini72fc2642022-12-04 10:03:57 -050018 * If there is a need to operate slower, define CFG_FPGA_DELAY in
Stefan Roesef0ff4692006-08-15 14:15:51 +020019 * the board config file to slow things down.
20 */
Tom Rini72fc2642022-12-04 10:03:57 -050021#ifndef CFG_FPGA_DELAY
22#define CFG_FPGA_DELAY()
Stefan Roesef0ff4692006-08-15 14:15:51 +020023#endif
24
Tom Rini65cc0e22022-11-16 13:10:41 -050025#ifndef CFG_SYS_FPGA_WAIT
26#define CFG_SYS_FPGA_WAIT CONFIG_SYS_HZ / 10 /* 100 ms */
Stefan Roesef0ff4692006-08-15 14:15:51 +020027#endif
28
Wolfgang Denke6a857d2011-07-30 13:33:49 +000029static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize);
30static int CYC2_ps_dump(Altera_desc *desc, const void *buf, size_t bsize);
Stefan Roesef0ff4692006-08-15 14:15:51 +020031/* static int CYC2_ps_info( Altera_desc *desc ); */
Stefan Roesef0ff4692006-08-15 14:15:51 +020032
33/* ------------------------------------------------------------------------- */
34/* CYCLON2 Generic Implementation */
Wolfgang Denke6a857d2011-07-30 13:33:49 +000035int CYC2_load(Altera_desc *desc, const void *buf, size_t bsize)
Stefan Roesef0ff4692006-08-15 14:15:51 +020036{
37 int ret_val = FPGA_FAIL;
38
39 switch (desc->iface) {
40 case passive_serial:
Alexander Dahl29e58112022-10-07 14:19:59 +020041 log_debug("Launching Passive Serial Loader\n");
Alexander Dahlbb2c0fa2019-06-28 14:41:21 +020042 ret_val = CYC2_ps_load(desc, buf, bsize);
Stefan Roesef0ff4692006-08-15 14:15:51 +020043 break;
44
Michael Jonesee44fb22011-07-14 23:09:41 +000045 case fast_passive_parallel:
46 /* Fast Passive Parallel (FPP) and PS only differ in what is
47 * done in the write() callback. Use the existing PS load
48 * function for FPP, too.
49 */
Alexander Dahl29e58112022-10-07 14:19:59 +020050 log_debug("Launching Fast Passive Parallel Loader\n");
Michael Jonesee44fb22011-07-14 23:09:41 +000051 ret_val = CYC2_ps_load(desc, buf, bsize);
52 break;
53
Stefan Roesef0ff4692006-08-15 14:15:51 +020054 /* Add new interface types here */
55
56 default:
Alexander Dahlbb2c0fa2019-06-28 14:41:21 +020057 printf("%s: Unsupported interface type, %d\n",
58 __func__, desc->iface);
Stefan Roesef0ff4692006-08-15 14:15:51 +020059 }
60
61 return ret_val;
62}
63
Wolfgang Denke6a857d2011-07-30 13:33:49 +000064int CYC2_dump(Altera_desc *desc, const void *buf, size_t bsize)
Stefan Roesef0ff4692006-08-15 14:15:51 +020065{
66 int ret_val = FPGA_FAIL;
67
68 switch (desc->iface) {
69 case passive_serial:
Alexander Dahl29e58112022-10-07 14:19:59 +020070 log_debug("Launching Passive Serial Dump\n");
Alexander Dahlbb2c0fa2019-06-28 14:41:21 +020071 ret_val = CYC2_ps_dump(desc, buf, bsize);
Stefan Roesef0ff4692006-08-15 14:15:51 +020072 break;
73
74 /* Add new interface types here */
75
76 default:
Alexander Dahlbb2c0fa2019-06-28 14:41:21 +020077 printf("%s: Unsupported interface type, %d\n",
78 __func__, desc->iface);
Stefan Roesef0ff4692006-08-15 14:15:51 +020079 }
80
81 return ret_val;
82}
83
Alexander Dahlbb2c0fa2019-06-28 14:41:21 +020084int CYC2_info(Altera_desc *desc)
Stefan Roesef0ff4692006-08-15 14:15:51 +020085{
86 return FPGA_SUCCESS;
87}
88
Stefan Roesef0ff4692006-08-15 14:15:51 +020089/* ------------------------------------------------------------------------- */
Alexander Dahlbb2c0fa2019-06-28 14:41:21 +020090/* CYCLON2 Passive Serial Generic Implementation */
Wolfgang Denke6a857d2011-07-30 13:33:49 +000091static int CYC2_ps_load(Altera_desc *desc, const void *buf, size_t bsize)
Stefan Roesef0ff4692006-08-15 14:15:51 +020092{
93 int ret_val = FPGA_FAIL; /* assume the worst */
94 Altera_CYC2_Passive_Serial_fns *fn = desc->iface_fns;
95 int ret = 0;
96
Alexander Dahl29e58112022-10-07 14:19:59 +020097 log_debug("start with interface functions @ 0x%p\n", fn);
Stefan Roesef0ff4692006-08-15 14:15:51 +020098
99 if (fn) {
100 int cookie = desc->cookie; /* make a local copy */
101 unsigned long ts; /* timestamp */
102
Alexander Dahl29e58112022-10-07 14:19:59 +0200103 log_debug("Function Table:\n"
104 "ptr:\t0x%p\n"
105 "struct: 0x%p\n"
106 "config:\t0x%p\n"
107 "status:\t0x%p\n"
108 "write:\t0x%p\n"
109 "done:\t0x%p\n\n",
110 &fn, fn, fn->config, fn->status,
111 fn->write, fn->done);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
Alexander Dahlbb2c0fa2019-06-28 14:41:21 +0200113 printf("Loading FPGA Device %d...", cookie);
Stefan Roesef0ff4692006-08-15 14:15:51 +0200114#endif
115
116 /*
117 * Run the pre configuration function if there is one.
118 */
Alexander Dahlbb2c0fa2019-06-28 14:41:21 +0200119 if (*fn->pre)
Stefan Roesef0ff4692006-08-15 14:15:51 +0200120 (*fn->pre) (cookie);
Stefan Roesef0ff4692006-08-15 14:15:51 +0200121
122 /* Establish the initial state */
York Sun472d5462013-04-01 11:29:11 -0700123 (*fn->config) (false, true, cookie); /* De-assert nCONFIG */
Stephan Gatzkaa99c0402012-10-22 23:11:41 +0000124 udelay(100);
York Sun472d5462013-04-01 11:29:11 -0700125 (*fn->config) (true, true, cookie); /* Assert nCONFIG */
Stefan Roesef0ff4692006-08-15 14:15:51 +0200126
127 udelay(2); /* T_cfg > 2us */
128
129 /* Wait for nSTATUS to be asserted */
Alexander Dahlbb2c0fa2019-06-28 14:41:21 +0200130 ts = get_timer(0); /* get current time */
Stefan Roesef0ff4692006-08-15 14:15:51 +0200131 do {
Tom Rini72fc2642022-12-04 10:03:57 -0500132 CFG_FPGA_DELAY();
Tom Rini65cc0e22022-11-16 13:10:41 -0500133 if (get_timer(ts) > CFG_SYS_FPGA_WAIT) {
Alexander Dahlbb2c0fa2019-06-28 14:41:21 +0200134 /* check the time */
135 puts("** Timeout waiting for STATUS to go high.\n");
Stefan Roesef0ff4692006-08-15 14:15:51 +0200136 (*fn->abort) (cookie);
137 return FPGA_FAIL;
138 }
139 } while (!(*fn->status) (cookie));
140
141 /* Get ready for the burn */
Tom Rini72fc2642022-12-04 10:03:57 -0500142 CFG_FPGA_DELAY();
Stefan Roesef0ff4692006-08-15 14:15:51 +0200143
York Sun472d5462013-04-01 11:29:11 -0700144 ret = (*fn->write) (buf, bsize, true, cookie);
Stefan Roesef0ff4692006-08-15 14:15:51 +0200145 if (ret) {
Alexander Dahlbb2c0fa2019-06-28 14:41:21 +0200146 puts("** Write failed.\n");
Stefan Roesef0ff4692006-08-15 14:15:51 +0200147 (*fn->abort) (cookie);
148 return FPGA_FAIL;
149 }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
Stefan Roesef0ff4692006-08-15 14:15:51 +0200151 puts(" OK? ...");
152#endif
153
Tom Rini72fc2642022-12-04 10:03:57 -0500154 CFG_FPGA_DELAY();
Stefan Roesef0ff4692006-08-15 14:15:51 +0200155
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
Alexander Dahlbb2c0fa2019-06-28 14:41:21 +0200157 putc(' '); /* terminate the dotted line */
Stefan Roesef0ff4692006-08-15 14:15:51 +0200158#endif
159
Alexander Dahl3911b192019-06-28 14:41:22 +0200160 /*
161 * Checking FPGA's CONF_DONE signal - correctly booted ?
162 */
Stefan Roesef0ff4692006-08-15 14:15:51 +0200163
Alexander Dahl3911b192019-06-28 14:41:22 +0200164 if (!(*fn->done) (cookie)) {
165 puts("** Booting failed! CONF_DONE is still deasserted.\n");
166 (*fn->abort) (cookie);
167 return FPGA_FAIL;
168 }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
Alexander Dahl3911b192019-06-28 14:41:22 +0200170 puts(" OK\n");
Stefan Roesef0ff4692006-08-15 14:15:51 +0200171#endif
172
Alexander Dahl3911b192019-06-28 14:41:22 +0200173 ret_val = FPGA_SUCCESS;
Stefan Roesef0ff4692006-08-15 14:15:51 +0200174
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
Alexander Dahl3911b192019-06-28 14:41:22 +0200176 if (ret_val == FPGA_SUCCESS)
177 puts("Done.\n");
178 else
179 puts("Fail.\n");
Stefan Roesef0ff4692006-08-15 14:15:51 +0200180#endif
Stefan Roesef0ff4692006-08-15 14:15:51 +0200181
Alexander Dahlb283d6b2019-06-28 14:41:23 +0200182 /*
183 * Run the post configuration function if there is one.
184 */
185 if (*fn->post)
186 (*fn->post) (cookie);
Stefan Roesef0ff4692006-08-15 14:15:51 +0200187 } else {
Alexander Dahlbb2c0fa2019-06-28 14:41:21 +0200188 printf("%s: NULL Interface function table!\n", __func__);
Stefan Roesef0ff4692006-08-15 14:15:51 +0200189 }
190
191 return ret_val;
192}
193
Wolfgang Denke6a857d2011-07-30 13:33:49 +0000194static int CYC2_ps_dump(Altera_desc *desc, const void *buf, size_t bsize)
Stefan Roesef0ff4692006-08-15 14:15:51 +0200195{
196 /* Readback is only available through the Slave Parallel and */
197 /* boundary-scan interfaces. */
Alexander Dahlbb2c0fa2019-06-28 14:41:21 +0200198 printf("%s: Passive Serial Dumping is unavailable\n", __func__);
Stefan Roesef0ff4692006-08-15 14:15:51 +0200199 return FPGA_FAIL;
200}