| Patrick Delaunay | 3d2d115 | 2018-03-12 10:46:17 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (C) 2018, STMicroelectronics - All Rights Reserved |
| 3 | * |
| 4 | * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | /* STM32MP157C ED1 and ED2 BOARD configuration |
| 8 | * 2x DDR3L 4Gb each, 16-bit, 533MHz, Single Die Package in flyby topology. |
| 9 | * Reference used NT5CC256M16DP-DI from NANYA |
| 10 | * |
| 11 | * DDR type / Platform DDR3/3L |
| 12 | * freq 533MHz |
| 13 | * width 32 |
| 14 | * datasheet 0 = MT41J256M16-187 / DDR3-1066 bin G |
| 15 | * DDR density 8 |
| 16 | * timing mode optimized |
| 17 | * Scheduling/QoS options : type = 2 |
| 18 | * address mapping : RBC |
| 19 | */ |
| 20 | |
| 21 | #define DDR_MEM_NAME "DDR3-1066 bin G 2x4Gb 533MHz v1.36" |
| 22 | #define DDR_MEM_SPEED 533 |
| 23 | #define DDR_MEM_SIZE 0x40000000 |
| 24 | |
| 25 | #define DDR_MSTR 0x00040401 |
| 26 | #define DDR_MRCTRL0 0x00000010 |
| 27 | #define DDR_MRCTRL1 0x00000000 |
| 28 | #define DDR_DERATEEN 0x00000000 |
| 29 | #define DDR_DERATEINT 0x00800000 |
| 30 | #define DDR_PWRCTL 0x00000000 |
| 31 | #define DDR_PWRTMG 0x00400010 |
| 32 | #define DDR_HWLPCTL 0x00000000 |
| 33 | #define DDR_RFSHCTL0 0x00210000 |
| 34 | #define DDR_RFSHCTL3 0x00000000 |
| 35 | #define DDR_RFSHTMG 0x0081008B |
| 36 | #define DDR_CRCPARCTL0 0x00000000 |
| 37 | #define DDR_DRAMTMG0 0x121B2414 |
| 38 | #define DDR_DRAMTMG1 0x000A041C |
| 39 | #define DDR_DRAMTMG2 0x0608090F |
| 40 | #define DDR_DRAMTMG3 0x0050400C |
| 41 | #define DDR_DRAMTMG4 0x08040608 |
| 42 | #define DDR_DRAMTMG5 0x06060403 |
| 43 | #define DDR_DRAMTMG6 0x02020002 |
| 44 | #define DDR_DRAMTMG7 0x00000202 |
| 45 | #define DDR_DRAMTMG8 0x00001005 |
| 46 | #define DDR_DRAMTMG14 0x000000A0 |
| 47 | #define DDR_ZQCTL0 0xC2000040 |
| 48 | #define DDR_DFITMG0 0x02060105 |
| 49 | #define DDR_DFITMG1 0x00000202 |
| 50 | #define DDR_DFILPCFG0 0x07000000 |
| 51 | #define DDR_DFIUPD0 0xC0400003 |
| 52 | #define DDR_DFIUPD1 0x00000000 |
| 53 | #define DDR_DFIUPD2 0x00000000 |
| 54 | #define DDR_DFIPHYMSTR 0x00000000 |
| 55 | #define DDR_ADDRMAP1 0x00080808 |
| 56 | #define DDR_ADDRMAP2 0x00000000 |
| 57 | #define DDR_ADDRMAP3 0x00000000 |
| 58 | #define DDR_ADDRMAP4 0x00001F1F |
| 59 | #define DDR_ADDRMAP5 0x07070707 |
| 60 | #define DDR_ADDRMAP6 0x0F070707 |
| 61 | #define DDR_ADDRMAP9 0x00000000 |
| 62 | #define DDR_ADDRMAP10 0x00000000 |
| 63 | #define DDR_ADDRMAP11 0x00000000 |
| 64 | #define DDR_ODTCFG 0x06000600 |
| 65 | #define DDR_ODTMAP 0x00000001 |
| 66 | #define DDR_SCHED 0x00001201 |
| 67 | #define DDR_SCHED1 0x00000000 |
| 68 | #define DDR_PERFHPR1 0x01000001 |
| 69 | #define DDR_PERFLPR1 0x08000200 |
| 70 | #define DDR_PERFWR1 0x08000400 |
| 71 | #define DDR_DBG0 0x00000000 |
| 72 | #define DDR_DBG1 0x00000000 |
| 73 | #define DDR_DBGCMD 0x00000000 |
| 74 | #define DDR_POISONCFG 0x00000000 |
| 75 | #define DDR_PCCFG 0x00000010 |
| 76 | #define DDR_PCFGR_0 0x00010000 |
| 77 | #define DDR_PCFGW_0 0x00000000 |
| 78 | #define DDR_PCFGQOS0_0 0x02100B03 |
| 79 | #define DDR_PCFGQOS1_0 0x00800100 |
| 80 | #define DDR_PCFGWQOS0_0 0x01100B03 |
| 81 | #define DDR_PCFGWQOS1_0 0x01000200 |
| 82 | #define DDR_PCFGR_1 0x00010000 |
| 83 | #define DDR_PCFGW_1 0x00000000 |
| 84 | #define DDR_PCFGQOS0_1 0x02100B03 |
| 85 | #define DDR_PCFGQOS1_1 0x00800100 |
| 86 | #define DDR_PCFGWQOS0_1 0x01100B03 |
| 87 | #define DDR_PCFGWQOS1_1 0x01000200 |
| 88 | #define DDR_PGCR 0x01442E02 |
| 89 | #define DDR_PTR0 0x0022AA5B |
| 90 | #define DDR_PTR1 0x04841104 |
| 91 | #define DDR_PTR2 0x042DA068 |
| 92 | #define DDR_ACIOCR 0x10400812 |
| 93 | #define DDR_DXCCR 0x00000C40 |
| 94 | #define DDR_DSGCR 0xF200001F |
| 95 | #define DDR_DCR 0x0000000B |
| 96 | #define DDR_DTPR0 0x38D488D0 |
| 97 | #define DDR_DTPR1 0x098B00D8 |
| 98 | #define DDR_DTPR2 0x10023600 |
| 99 | #define DDR_MR0 0x00000840 |
| 100 | #define DDR_MR1 0x00000000 |
| 101 | #define DDR_MR2 0x00000208 |
| 102 | #define DDR_MR3 0x00000000 |
| 103 | #define DDR_ODTCR 0x00010000 |
| 104 | #define DDR_ZQ0CR1 0x0000005B |
| 105 | #define DDR_DX0GCR 0x0000CE81 |
| 106 | #define DDR_DX0DLLCR 0x40000000 |
| 107 | #define DDR_DX0DQTR 0xFFFFFFFF |
| 108 | #define DDR_DX0DQSTR 0x3DB02000 |
| 109 | #define DDR_DX1GCR 0x0000CE81 |
| 110 | #define DDR_DX1DLLCR 0x40000000 |
| 111 | #define DDR_DX1DQTR 0xFFFFFFFF |
| 112 | #define DDR_DX1DQSTR 0x3DB02000 |
| 113 | #define DDR_DX2GCR 0x0000CE81 |
| 114 | #define DDR_DX2DLLCR 0x40000000 |
| 115 | #define DDR_DX2DQTR 0xFFFFFFFF |
| 116 | #define DDR_DX2DQSTR 0x3DB02000 |
| 117 | #define DDR_DX3GCR 0x0000CE81 |
| 118 | #define DDR_DX3DLLCR 0x40000000 |
| 119 | #define DDR_DX3DQTR 0xFFFFFFFF |
| 120 | #define DDR_DX3DQSTR 0x3DB02000 |
| 121 | |
| 122 | #include "stm32mp15-ddr.dtsi" |