blob: 1ef4de41efbab706a3ec64821c26410062141de9 [file] [log] [blame]
Kumar Gala80d0b6a2008-01-17 00:32:17 -06001/*
2 * Copyright 2008 Freescale Semiconductor, Inc.
3 *
4 * (C) Copyright 2000
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <common.h>
27#include <asm/mmu.h>
28
29struct fsl_e_tlb_entry tlb_table[] = {
30 /* TLB 0 - for temp stack in cache */
31 SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
32 MAS3_SX|MAS3_SW|MAS3_SR, 0,
33 0, 0, BOOKE_PAGESZ_4K, 0),
34 SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
35 MAS3_SX|MAS3_SW|MAS3_SR, 0,
36 0, 0, BOOKE_PAGESZ_4K, 0),
37 SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
38 MAS3_SX|MAS3_SW|MAS3_SR, 0,
39 0, 0, BOOKE_PAGESZ_4K, 0),
40 SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
41 MAS3_SX|MAS3_SW|MAS3_SR, 0,
42 0, 0, BOOKE_PAGESZ_4K, 0),
43
44 /* TLB 1 Initializations */
45 /*
46 * TLB 0, 1: 128M Non-cacheable, guarded
47 * 0xf8000000 128M FLASH
48 * Out of reset this entry is only 4K.
49 */
50 SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x4000000, CFG_FLASH_BASE + 0x4000000,
51 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
52 0, 0, BOOKE_PAGESZ_64M, 1),
53
54 SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
55 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
56 0, 1, BOOKE_PAGESZ_64M, 1),
57
58 /*
59 * TLB 2: 1G Non-cacheable, guarded
60 * 0x80000000 1G PCI1/PCIE 8,9,a,b
61 */
62 SET_TLB_ENTRY(1, CFG_PCI_PHYS, CFG_PCI_PHYS,
63 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
64 0, 2, BOOKE_PAGESZ_1G, 1),
65
66 /*
67 * TLB 3, 4: 512M Non-cacheable, guarded
68 * 0xc0000000 1G PCI2
69 */
70 SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS, CFG_PCI2_MEM_PHYS,
71 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
72 0, 3, BOOKE_PAGESZ_256M, 1),
73
74 SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS + 0x10000000, CFG_PCI2_MEM_PHYS + 0x10000000,
75 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
76 0, 4, BOOKE_PAGESZ_256M, 1),
77
78 /*
79 * TLB 5: 64M Non-cacheable, guarded
80 * 0xe000_0000 1M CCSRBAR
81 * 0xe200_0000 1M PCI1 IO
82 * 0xe210_0000 1M PCI2 IO
83 * 0xe300_0000 1M PCIe IO
84 */
Kumar Galaf69766e2008-01-30 14:55:14 -060085 SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
Kumar Gala80d0b6a2008-01-17 00:32:17 -060086 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
87 0, 5, BOOKE_PAGESZ_64M, 1),
88};
89
90int num_tlb_entries = ARRAY_SIZE(tlb_table);