blob: fe8ec1eab848e79ec06cf8f05a301b1510336937 [file] [log] [blame]
Dave Liu8bd522c2008-01-11 18:48:24 +08001/*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 *
4 * Authors: Nick.Spence@freescale.com
5 * Wilson.Lo@freescale.com
6 * scottwood@freescale.com
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <mpc83xx.h>
29#include <spd_sdram.h>
30
31#include <asm/bitops.h>
32#include <asm/io.h>
33
34#include <asm/processor.h>
35
36DECLARE_GLOBAL_DATA_PTR;
37
38static void resume_from_sleep(void)
39{
40 u32 magic = *(u32 *)0;
41
42 typedef void (*func_t)(void);
43 func_t resume = *(func_t *)4;
44
45 if (magic == 0xf5153ae5)
46 resume();
47
48 gd->flags &= ~GD_FLG_SILENT;
49 puts("\nResume from sleep failed: bad magic word\n");
50}
51
52/* Fixed sdram init -- doesn't use serial presence detect.
53 *
54 * This is useful for faster booting in configs where the RAM is unlikely
55 * to be changed, or for things like NAND booting where space is tight.
56 */
Anton Vorontsov2e950042009-11-24 20:12:12 +030057#ifndef CONFIG_SYS_RAMBOOT
Dave Liu8bd522c2008-01-11 18:48:24 +080058static long fixed_sdram(void)
59{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
61 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
Dave Liu8bd522c2008-01-11 18:48:24 +080062 u32 msize_log2 = __ilog2(msize);
63
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
Dave Liu8bd522c2008-01-11 18:48:24 +080065 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
Dave Liu8bd522c2008-01-11 18:48:24 +080067
68 /*
69 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
70 * or the DDR2 controller may fail to initialize correctly.
71 */
Anton Vorontsov2e950042009-11-24 20:12:12 +030072 __udelay(50000);
Dave Liu8bd522c2008-01-11 18:48:24 +080073
74 im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
Dave Liu8bd522c2008-01-11 18:48:24 +080076
77 /* Currently we use only one CS, so disable the other bank. */
78 im->ddr.cs_config[1] = 0;
79
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
81 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
82 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
83 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
84 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
Dave Liu8bd522c2008-01-11 18:48:24 +080085
86 if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI;
Dave Liu8bd522c2008-01-11 18:48:24 +080088 else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
Dave Liu8bd522c2008-01-11 18:48:24 +080090
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
92 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
93 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
Dave Liu8bd522c2008-01-11 18:48:24 +080094
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
Dave Liu8bd522c2008-01-11 18:48:24 +080096 sync();
97
98 /* enable DDR controller */
99 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
100 sync();
101
102 return msize;
103}
Anton Vorontsov2e950042009-11-24 20:12:12 +0300104#else
105static long fixed_sdram(void)
106{
107 return CONFIG_SYS_DDR_SIZE * 1024 * 1024;
108}
109#endif /* CONFIG_SYS_RAMBOOT */
Dave Liu8bd522c2008-01-11 18:48:24 +0800110
Becky Bruce9973e3c2008-06-09 16:03:40 -0500111phys_size_t initdram(int board_type)
Dave Liu8bd522c2008-01-11 18:48:24 +0800112{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
Dave Liu8bd522c2008-01-11 18:48:24 +0800114 u32 msize;
115
116 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
117 return -1;
118
119 /* DDR SDRAM */
120 msize = fixed_sdram();
121
122 if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
123 resume_from_sleep();
124
125 /* return total bus SDRAM size(bytes) -- DDR */
126 return msize;
127}