blob: a28c6ace26de5620b9ffc4b95e5aae8a8e322eb9 [file] [log] [blame]
wdenk0669d4d2002-09-17 20:57:30 +00001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * mpc8xx.h
26 *
27 * MPC8xx specific definitions
28 */
29
30#ifndef __MPCXX_H__
31#define __MPCXX_H__
32
33
34/*-----------------------------------------------------------------------
35 * Exception offsets (PowerPC standard)
36 */
37#define EXC_OFF_SYS_RESET 0x0100 /* System reset */
38
39
40/*-----------------------------------------------------------------------
41 * SYPCR - System Protection Control Register 11-9
42 */
43#define SYPCR_SWTC 0xffff0000 /* Software Watchdog Timer Count */
44#define SYPCR_BMT 0x0000ff00 /* Bus Monitor Timing */
45#define SYPCR_BME 0x00000080 /* Bus Monitor Enable */
46#define SYPCR_SWF 0x00000008 /* Software Watchdog Freeze */
47#define SYPCR_SWE 0x00000004 /* Software Watchdog Enable */
48#define SYPCR_SWRI 0x00000002 /* Software Watchdog Reset/Int Select */
49#define SYPCR_SWP 0x00000001 /* Software Watchdog Prescale */
50
51/*-----------------------------------------------------------------------
52 * SIUMCR - SIU Module Configuration Register 11-6
53 */
54#define SIUMCR_EARB 0x80000000 /* External Arbitration */
55#define SIUMCR_EARP0 0x00000000 /* External Arbi. Request priority 0 */
56#define SIUMCR_EARP1 0x10000000 /* External Arbi. Request priority 1 */
57#define SIUMCR_EARP2 0x20000000 /* External Arbi. Request priority 2 */
58#define SIUMCR_EARP3 0x30000000 /* External Arbi. Request priority 3 */
59#define SIUMCR_EARP4 0x40000000 /* External Arbi. Request priority 4 */
60#define SIUMCR_EARP5 0x50000000 /* External Arbi. Request priority 5 */
61#define SIUMCR_EARP6 0x60000000 /* External Arbi. Request priority 6 */
62#define SIUMCR_EARP7 0x70000000 /* External Arbi. Request priority 7 */
63#define SIUMCR_DSHW 0x00800000 /* Data Showcycles */
64#define SIUMCR_DBGC00 0x00000000 /* Debug pins configuration */
65#define SIUMCR_DBGC01 0x00200000 /* - " - */
66#define SIUMCR_DBGC10 0x00400000 /* - " - */
67#define SIUMCR_DBGC11 0x00600000 /* - " - */
68#define SIUMCR_DBPC00 0x00000000 /* Debug Port pins Config. */
69#define SIUMCR_DBPC01 0x00080000 /* - " - */
70#define SIUMCR_DBPC10 0x00100000 /* - " - */
71#define SIUMCR_DBPC11 0x00180000 /* - " - */
72#define SIUMCR_FRC 0x00020000 /* FRZ pin Configuration */
73#define SIUMCR_DLK 0x00010000 /* Debug Register Lock */
74#define SIUMCR_PNCS 0x00008000 /* Parity Non-mem Crtl reg */
75#define SIUMCR_OPAR 0x00004000 /* Odd Parity */
76#define SIUMCR_DPC 0x00002000 /* Data Parity pins Config. */
77#define SIUMCR_MPRE 0x00001000 /* Multi CPU Reserva. Enable */
78#define SIUMCR_MLRC00 0x00000000 /* Multi Level Reserva. Ctrl */
79#define SIUMCR_MLRC01 0x00000400 /* - " - */
80#define SIUMCR_MLRC10 0x00000800 /* - " - */
81#define SIUMCR_MLRC11 0x00000c00 /* - " - */
82#define SIUMCR_AEME 0x00000200 /* Asynchro External Master */
83#define SIUMCR_SEME 0x00000100 /* Synchro External Master */
84#define SIUMCR_BSC 0x00000080 /* Byte Select Configuration */
85#define SIUMCR_GB5E 0x00000040 /* GPL_B(5) Enable */
86#define SIUMCR_B2DD 0x00000020 /* Bank 2 Double Drive */
87#define SIUMCR_B3DD 0x00000010 /* Bank 3 Double Drive */
88
89/*-----------------------------------------------------------------------
90 * TBSCR - Time Base Status and Control Register 11-26
91 */
92#define TBSCR_TBIRQ7 0x8000 /* Time Base Interrupt Request 7 */
93#define TBSCR_TBIRQ6 0x4000 /* Time Base Interrupt Request 6 */
94#define TBSCR_TBIRQ5 0x2000 /* Time Base Interrupt Request 5 */
95#define TBSCR_TBIRQ4 0x1000 /* Time Base Interrupt Request 4 */
96#define TBSCR_TBIRQ3 0x0800 /* Time Base Interrupt Request 3 */
97#define TBSCR_TBIRQ2 0x0400 /* Time Base Interrupt Request 2 */
98#define TBSCR_TBIRQ1 0x0200 /* Time Base Interrupt Request 1 */
99#define TBSCR_TBIRQ0 0x0100 /* Time Base Interrupt Request 0 */
100#if 0 /* already in asm/8xx_immap.h */
101#define TBSCR_REFA 0x0080 /* Reference Interrupt Status A */
102#define TBSCR_REFB 0x0040 /* Reference Interrupt Status B */
103#define TBSCR_REFAE 0x0008 /* Second Interrupt Enable A */
104#define TBSCR_REFBE 0x0004 /* Second Interrupt Enable B */
105#define TBSCR_TBF 0x0002 /* Time Base Freeze */
106#define TBSCR_TBE 0x0001 /* Time Base Enable */
107#endif
108
109/*-----------------------------------------------------------------------
110 * PISCR - Periodic Interrupt Status and Control Register 11-31
111 */
112#undef PISCR_PIRQ /* TBD */
113#define PISCR_PITF 0x0002 /* Periodic Interrupt Timer Freeze */
114#if 0 /* already in asm/8xx_immap.h */
115#define PISCR_PS 0x0080 /* Periodic interrupt Status */
116#define PISCR_PIE 0x0004 /* Periodic Interrupt Enable */
117#define PISCR_PTE 0x0001 /* Periodic Timer Enable */
118#endif
119
120/*-----------------------------------------------------------------------
121 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
122 */
123#define PLPRCR_MF_MSK 0xfff00000 /* Multiplication factor bits */
124#define PLPRCR_MF_SHIFT 0x00000014 /* Multiplication factor shift value */
125#define PLPRCR_SPLSS 0x00008000 /* SPLL Lock Status Sticky bit */
126#define PLPRCR_TEXPS 0x00004000 /* TEXP Status */
127#define PLPRCR_TMIST 0x00001000 /* Timers Interrupt Status */
128#define PLPRCR_CSRC 0x00000400 /* Clock Source */
129#define PLPRCR_LPM_MSK 0x00000300 /* Low Power Mode mask */
130#define PLPRCR_LPM_NORMAL 0x00000000 /* normal power management mode */
131#define PLPRCR_LPM_DOZE 0x00000100 /* doze power management mode */
132#define PLPRCR_LPM_SLEEP 0x00000200 /* sleep power management mode */
133#define PLPRCR_LPM_DEEP_SLEEP 0x00000300 /* deep sleep power mgt mode */
134#define PLPRCR_LPM_DOWN 0x00000300 /* down power management mode */
135#define PLPRCR_CSR 0x00000080 /* CheskStop Reset value */
136#define PLPRCR_LOLRE 0x00000040 /* Loss Of Lock Reset Enable */
137#define PLPRCR_FIOPD 0x00000020 /* Force I/O Pull Down */
138
139/*-----------------------------------------------------------------------
140 * SCCR - System Clock and reset Control Register 15-27
141 */
142#define SCCR_COM00 0x00000000 /* full strength CLKOUT output buffer */
143#define SCCR_COM01 0x20000000 /* half strength CLKOUT output buffer */
144#define SCCR_COM10 0x40000000 /* reserved */
145#define SCCR_COM11 0x60000000 /* CLKOUT output buffer disabled */
146#define SCCR_TBS 0x02000000 /* Time Base Source */
147#define SCCR_RTDIV 0x01000000 /* RTC Clock Divide */
148#define SCCR_RTSEL 0x00800000 /* RTC circuit input source select */
149#define SCCR_CRQEN 0x00400000 /* CPM Request Enable */
150#define SCCR_PRQEN 0x00200000 /* Power Management Request Enable */
151#define SCCR_EBDF00 0x00000000 /* CLKOUT is GCLK2 / 1 (normal op.) */
152#define SCCR_EBDF01 0x00020000 /* CLKOUT is GCLK2 / 2 */
153#define SCCR_EBDF10 0x00040000 /* reserved */
154#define SCCR_EBDF11 0x00060000 /* reserved */
155#define SCCR_DFSYNC00 0x00000000 /* SyncCLK division by 1 (normal op.) */
156#define SCCR_DFSYNC01 0x00002000 /* SyncCLK division by 4 */
157#define SCCR_DFSYNC10 0x00004000 /* SyncCLK division by 16 */
158#define SCCR_DFSYNC11 0x00006000 /* SyncCLK division by 64 */
159#define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 1 (normal op.) */
160#define SCCR_DFBRG01 0x00000800 /* BRGCLK division by 4 */
161#define SCCR_DFBRG10 0x00001000 /* BRGCLK division by 16 */
162#define SCCR_DFBRG11 0x00001800 /* BRGCLK division by 64 */
163#define SCCR_DFNL000 0x00000000 /* Division by 2 (default = minimum) */
164#define SCCR_DFNL111 0x00000700 /* Division by 256 (maximum) */
165#define SCCR_DFNH000 0x00000000 /* Division by 1 (default = minimum) */
166#define SCCR_DFNH110 0x000000D0 /* Division by 64 (maximum) */
167#define SCCR_DFNH111 0x000000E0 /* reserved */
168#define SCCR_DFLCD000 0x00000000 /* Division by 1 (default = minimum) */
169#define SCCR_DFLCD001 0x00000004 /* Division by 2 */
170#define SCCR_DFLCD010 0x00000008 /* Division by 4 */
171#define SCCR_DFLCD011 0x0000000C /* Division by 8 */
172#define SCCR_DFLCD100 0x00000010 /* Division by 16 */
173#define SCCR_DFLCD101 0x00000014 /* Division by 32 */
174#define SCCR_DFLCD110 0x00000018 /* Division by 64 (maximum) */
175#define SCCR_DFLCD111 0x0000001C /* reserved */
176#define SCCR_DFALCD00 0x00000000 /* Division by 1 (default = minimum) */
177#define SCCR_DFALCD01 0x00000001 /* Division by 3 */
178#define SCCR_DFALCD10 0x00000002 /* Division by 5 */
179#define SCCR_DFALCD11 0x00000003 /* Division by 7 (maximum) */
180
181
182/*-----------------------------------------------------------------------
183 * BR - Memory Controler: Base Register 16-9
184 */
185#define BR_BA_MSK 0xffff8000 /* Base Address Mask */
186#define BR_AT_MSK 0x00007000 /* Address Type Mask */
187#define BR_PS_MSK 0x00000c00 /* Port Size Mask */
188#define BR_PS_32 0x00000000 /* 32 bit port size */
189#define BR_PS_16 0x00000800 /* 16 bit port size */
190#define BR_PS_8 0x00000400 /* 8 bit port size */
191#define BR_PARE 0x00000200 /* Parity Enable */
192#define BR_WP 0x00000100 /* Write Protect */
193#define BR_MS_MSK 0x000000c0 /* Machine Select Mask */
194#define BR_MS_GPCM 0x00000000 /* G.P.C.M. Machine Select */
195#define BR_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */
196#define BR_MS_UPMB 0x000000c0 /* U.P.M.B Machine Select */
197#define BR_V 0x00000001 /* Bank Valid */
198
199/*-----------------------------------------------------------------------
200 * OR - Memory Controler: Option Register 16-11
201 */
202#define OR_AM_MSK 0xffff8000 /* Address Mask Mask */
203#define OR_ATM_MSK 0x00007000 /* Address Type Mask Mask */
204#define OR_CSNT_SAM 0x00000800 /* Chip Select Negation Time/ Start */
205 /* Address Multiplex */
206#define OR_ACS_MSK 0x00000600 /* Address to Chip Select Setup mask */
207#define OR_ACS_DIV1 0x00000000 /* CS is output at the same time */
208#define OR_ACS_DIV4 0x00000400 /* CS is output 1/4 a clock later */
209#define OR_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later */
210#define OR_G5LA 0x00000400 /* Output #GPL5 on #GPL_A5 */
211#define OR_G5LS 0x00000200 /* Drive #GPL high on falling edge of...*/
212#define OR_BI 0x00000100 /* Burst inhibit */
213#define OR_SCY_MSK 0x000000f0 /* Cycle Lenght in Clocks */
214#define OR_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */
215#define OR_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */
216#define OR_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */
217#define OR_SCY_3_CLK 0x00000030 /* 3 clock cycles wait states */
218#define OR_SCY_4_CLK 0x00000040 /* 4 clock cycles wait states */
219#define OR_SCY_5_CLK 0x00000050 /* 5 clock cycles wait states */
220#define OR_SCY_6_CLK 0x00000060 /* 6 clock cycles wait states */
221#define OR_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */
222#define OR_SCY_8_CLK 0x00000080 /* 8 clock cycles wait states */
223#define OR_SCY_9_CLK 0x00000090 /* 9 clock cycles wait states */
224#define OR_SCY_10_CLK 0x000000a0 /* 10 clock cycles wait states */
225#define OR_SCY_11_CLK 0x000000b0 /* 11 clock cycles wait states */
226#define OR_SCY_12_CLK 0x000000c0 /* 12 clock cycles wait states */
227#define OR_SCY_13_CLK 0x000000d0 /* 13 clock cycles wait states */
228#define OR_SCY_14_CLK 0x000000e0 /* 14 clock cycles wait states */
229#define OR_SCY_15_CLK 0x000000f0 /* 15 clock cycles wait states */
230#define OR_SETA 0x00000008 /* External Transfer Acknowledge */
231#define OR_TRLX 0x00000004 /* Timing Relaxed */
232#define OR_EHTR 0x00000002 /* Extended Hold Time on Read */
233
234
235/*-----------------------------------------------------------------------
236 * MPTPR - Memory Periodic Timer Prescaler Register 16-17
237 */
238#define MPTPR_PTP_MSK 0xff00 /* Periodic Timers Prescaler Mask */
239#define MPTPR_PTP_DIV2 0x2000 /* BRGCLK divided by 2 */
240#define MPTPR_PTP_DIV4 0x1000 /* BRGCLK divided by 4 */
241#define MPTPR_PTP_DIV8 0x0800 /* BRGCLK divided by 8 */
242#define MPTPR_PTP_DIV16 0x0400 /* BRGCLK divided by 16 */
243#define MPTPR_PTP_DIV32 0x0200 /* BRGCLK divided by 32 */
244#define MPTPR_PTP_DIV64 0x0100 /* BRGCLK divided by 64 */
245
246/*-----------------------------------------------------------------------
247 * MCR - Memory Command Register
248 */
249#define MCR_OP_WRITE 0x00000000 /* WRITE command */
250#define MCR_OP_READ 0x40000000 /* READ command */
251#define MCR_OP_RUN 0x80000000 /* RUN command */
252#define MCR_UPM_A 0x00000000 /* Select UPM A */
253#define MCR_UPM_B 0x00800000 /* Select UPM B */
254#define MCR_MB_CS0 0x00000000 /* Use Chip Select /CS0 */
255#define MCR_MB_CS1 0x00002000 /* Use Chip Select /CS1 */
256#define MCR_MB_CS2 0x00004000 /* Use Chip Select /CS2 */
257#define MCR_MB_CS3 0x00006000 /* Use Chip Select /CS3 */
258#define MCR_MB_CS4 0x00008000 /* Use Chip Select /CS4 */
259#define MCR_MB_CS5 0x0000A000 /* Use Chip Select /CS5 */
260#define MCR_MB_CS6 0x0000C000 /* Use Chip Select /CS6 */
261#define MCR_MB_CS7 0x0000E000 /* Use Chip Select /CS7 */
262#define MCR_MLCF(n) (((n)&0xF)<<8) /* Memory Command Loop Count Field */
263#define MCR_MAD(addr) ((addr)&0x3F) /* Memory Array Index */
264
265/*-----------------------------------------------------------------------
266 * Machine A Mode Register 16-13
267 */
268#define MAMR_PTA_MSK 0xff000000 /* Periodic Timer A period mask */
269#define MAMR_PTA_SHIFT 0x00000018 /* Periodic Timer A period shift */
270#define MAMR_PTAE 0x00800000 /* Periodic Timer A Enable */
271#define MAMR_AMA_MSK 0x00700000 /* Addess Multiplexing size A */
272#define MAMR_AMA_TYPE_0 0x00000000 /* Addess Multiplexing Type 0 */
273#define MAMR_AMA_TYPE_1 0x00100000 /* Addess Multiplexing Type 1 */
274#define MAMR_AMA_TYPE_2 0x00200000 /* Addess Multiplexing Type 2 */
275#define MAMR_AMA_TYPE_3 0x00300000 /* Addess Multiplexing Type 3 */
276#define MAMR_AMA_TYPE_4 0x00400000 /* Addess Multiplexing Type 4 */
277#define MAMR_AMA_TYPE_5 0x00500000 /* Addess Multiplexing Type 5 */
278#define MAMR_DSA_MSK 0x00060000 /* Disable Timer period mask */
279#define MAMR_DSA_1_CYCL 0x00000000 /* 1 cycle Disable Period */
280#define MAMR_DSA_2_CYCL 0x00020000 /* 2 cycle Disable Period */
281#define MAMR_DSA_3_CYCL 0x00040000 /* 3 cycle Disable Period */
282#define MAMR_DSA_4_CYCL 0x00060000 /* 4 cycle Disable Period */
283#define MAMR_G0CLA_MSK 0x0000e000 /* General Line 0 Control A */
284#define MAMR_G0CLA_A12 0x00000000 /* General Line 0 : A12 */
285#define MAMR_G0CLA_A11 0x00002000 /* General Line 0 : A11 */
286#define MAMR_G0CLA_A10 0x00004000 /* General Line 0 : A10 */
287#define MAMR_G0CLA_A9 0x00006000 /* General Line 0 : A9 */
288#define MAMR_G0CLA_A8 0x00008000 /* General Line 0 : A8 */
289#define MAMR_G0CLA_A7 0x0000a000 /* General Line 0 : A7 */
290#define MAMR_G0CLA_A6 0x0000c000 /* General Line 0 : A6 */
291#define MAMR_G0CLA_A5 0x0000e000 /* General Line 0 : A5 */
292#define MAMR_GPL_A4DIS 0x00001000 /* GPL_A4 ouput line Disable */
293#define MAMR_RLFA_MSK 0x00000f00 /* Read Loop Field A mask */
294#define MAMR_RLFA_1X 0x00000100 /* The Read Loop is executed 1 time */
295#define MAMR_RLFA_2X 0x00000200 /* The Read Loop is executed 2 times */
296#define MAMR_RLFA_3X 0x00000300 /* The Read Loop is executed 3 times */
297#define MAMR_RLFA_4X 0x00000400 /* The Read Loop is executed 4 times */
298#define MAMR_RLFA_5X 0x00000500 /* The Read Loop is executed 5 times */
299#define MAMR_RLFA_6X 0x00000600 /* The Read Loop is executed 6 times */
300#define MAMR_RLFA_7X 0x00000700 /* The Read Loop is executed 7 times */
301#define MAMR_RLFA_8X 0x00000800 /* The Read Loop is executed 8 times */
302#define MAMR_RLFA_9X 0x00000900 /* The Read Loop is executed 9 times */
303#define MAMR_RLFA_10X 0x00000a00 /* The Read Loop is executed 10 times */
304#define MAMR_RLFA_11X 0x00000b00 /* The Read Loop is executed 11 times */
305#define MAMR_RLFA_12X 0x00000c00 /* The Read Loop is executed 12 times */
306#define MAMR_RLFA_13X 0x00000d00 /* The Read Loop is executed 13 times */
307#define MAMR_RLFA_14X 0x00000e00 /* The Read Loop is executed 14 times */
308#define MAMR_RLFA_15X 0x00000f00 /* The Read Loop is executed 15 times */
309#define MAMR_RLFA_16X 0x00000000 /* The Read Loop is executed 16 times */
310#define MAMR_WLFA_MSK 0x000000f0 /* Write Loop Field A mask */
311#define MAMR_WLFA_1X 0x00000010 /* The Write Loop is executed 1 time */
312#define MAMR_WLFA_2X 0x00000020 /* The Write Loop is executed 2 times */
313#define MAMR_WLFA_3X 0x00000030 /* The Write Loop is executed 3 times */
314#define MAMR_WLFA_4X 0x00000040 /* The Write Loop is executed 4 times */
315#define MAMR_WLFA_5X 0x00000050 /* The Write Loop is executed 5 times */
316#define MAMR_WLFA_6X 0x00000060 /* The Write Loop is executed 6 times */
317#define MAMR_WLFA_7X 0x00000070 /* The Write Loop is executed 7 times */
318#define MAMR_WLFA_8X 0x00000080 /* The Write Loop is executed 8 times */
319#define MAMR_WLFA_9X 0x00000090 /* The Write Loop is executed 9 times */
320#define MAMR_WLFA_10X 0x000000a0 /* The Write Loop is executed 10 times */
321#define MAMR_WLFA_11X 0x000000b0 /* The Write Loop is executed 11 times */
322#define MAMR_WLFA_12X 0x000000c0 /* The Write Loop is executed 12 times */
323#define MAMR_WLFA_13X 0x000000d0 /* The Write Loop is executed 13 times */
324#define MAMR_WLFA_14X 0x000000e0 /* The Write Loop is executed 14 times */
325#define MAMR_WLFA_15X 0x000000f0 /* The Write Loop is executed 15 times */
326#define MAMR_WLFA_16X 0x00000000 /* The Write Loop is executed 16 times */
327#define MAMR_TLFA_MSK 0x0000000f /* Timer Loop Field A mask */
328#define MAMR_TLFA_1X 0x00000001 /* The Timer Loop is executed 1 time */
329#define MAMR_TLFA_2X 0x00000002 /* The Timer Loop is executed 2 times */
330#define MAMR_TLFA_3X 0x00000003 /* The Timer Loop is executed 3 times */
331#define MAMR_TLFA_4X 0x00000004 /* The Timer Loop is executed 4 times */
332#define MAMR_TLFA_5X 0x00000005 /* The Timer Loop is executed 5 times */
333#define MAMR_TLFA_6X 0x00000006 /* The Timer Loop is executed 6 times */
334#define MAMR_TLFA_7X 0x00000007 /* The Timer Loop is executed 7 times */
335#define MAMR_TLFA_8X 0x00000008 /* The Timer Loop is executed 8 times */
336#define MAMR_TLFA_9X 0x00000009 /* The Timer Loop is executed 9 times */
337#define MAMR_TLFA_10X 0x0000000a /* The Timer Loop is executed 10 times */
338#define MAMR_TLFA_11X 0x0000000b /* The Timer Loop is executed 11 times */
339#define MAMR_TLFA_12X 0x0000000c /* The Timer Loop is executed 12 times */
340#define MAMR_TLFA_13X 0x0000000d /* The Timer Loop is executed 13 times */
341#define MAMR_TLFA_14X 0x0000000e /* The Timer Loop is executed 14 times */
342#define MAMR_TLFA_15X 0x0000000f /* The Timer Loop is executed 15 times */
343#define MAMR_TLFA_16X 0x00000000 /* The Timer Loop is executed 16 times */
344
345/*-----------------------------------------------------------------------
346 * Machine B Mode Register 16-13
347 */
348#define MAMR_PTB_MSK 0xff000000 /* Periodic Timer B period mask */
349#define MAMR_PTB_SHIFT 0x00000018 /* Periodic Timer B period shift */
350#define MAMR_PTBE 0x00800000 /* Periodic Timer B Enable */
351#define MAMR_AMB_MSK 0x00700000 /* Addess Multiplex size B */
352#define MAMR_AMB_TYPE_0 0x00000000 /* Addess Multiplexing Type 0 */
353#define MAMR_AMB_TYPE_1 0x00100000 /* Addess Multiplexing Type 1 */
354#define MAMR_AMB_TYPE_2 0x00200000 /* Addess Multiplexing Type 2 */
355#define MAMR_AMB_TYPE_3 0x00300000 /* Addess Multiplexing Type 3 */
356#define MAMR_AMB_TYPE_4 0x00400000 /* Addess Multiplexing Type 4 */
357#define MAMR_AMB_TYPE_5 0x00500000 /* Addess Multiplexing Type 5 */
358#define MAMR_DSB_MSK 0x00060000 /* Disable Timer period mask */
359#define MAMR_DSB_1_CYCL 0x00000000 /* 1 cycle Disable Period */
360#define MAMR_DSB_2_CYCL 0x00020000 /* 2 cycle Disable Period */
361#define MAMR_DSB_3_CYCL 0x00040000 /* 3 cycle Disable Period */
362#define MAMR_DSB_4_CYCL 0x00060000 /* 4 cycle Disable Period */
363#define MAMR_G0CLB_MSK 0x0000e000 /* General Line 0 Control B */
364#define MAMR_G0CLB_A12 0x00000000 /* General Line 0 : A12 */
365#define MAMR_G0CLB_A11 0x00002000 /* General Line 0 : A11 */
366#define MAMR_G0CLB_A10 0x00004000 /* General Line 0 : A10 */
367#define MAMR_G0CLB_A9 0x00006000 /* General Line 0 : A9 */
368#define MAMR_G0CLB_A8 0x00008000 /* General Line 0 : A8 */
369#define MAMR_G0CLB_A7 0x0000a000 /* General Line 0 : A7 */
370#define MAMR_G0CLB_A6 0x0000b000 /* General Line 0 : A6 */
371#define MAMR_G0CLB_A5 0x0000e000 /* General Line 0 : A5 */
372#define MAMR_GPL_B4DIS 0x00001000 /* GPL_B4 ouput line Disable */
373#define MAMR_RLFB_MSK 0x00000f00 /* Read Loop Field B mask */
374#define MAMR_RLFB_1X 0x00000100 /* The Read Loop is executed 1 time */
375#define MAMR_RLFB_2X 0x00000200 /* The Read Loop is executed 2 times */
376#define MAMR_RLFB_3X 0x00000300 /* The Read Loop is executed 3 times */
377#define MAMR_RLFB_4X 0x00000400 /* The Read Loop is executed 4 times */
378#define MAMR_RLFB_5X 0x00000500 /* The Read Loop is executed 5 times */
379#define MAMR_RLFB_6X 0x00000600 /* The Read Loop is executed 6 times */
380#define MAMR_RLFB_7X 0x00000700 /* The Read Loop is executed 7 times */
381#define MAMR_RLFB_8X 0x00000800 /* The Read Loop is executed 8 times */
382#define MAMR_RLFB_9X 0x00000900 /* The Read Loop is executed 9 times */
383#define MAMR_RLFB_10X 0x00000a00 /* The Read Loop is executed 10 times */
384#define MAMR_RLFB_11X 0x00000b00 /* The Read Loop is executed 11 times */
385#define MAMR_RLFB_12X 0x00000c00 /* The Read Loop is executed 12 times */
386#define MAMR_RLFB_13X 0x00000d00 /* The Read Loop is executed 13 times */
387#define MAMR_RLFB_14X 0x00000e00 /* The Read Loop is executed 14 times */
388#define MAMR_RLFB_15X 0x00000f00 /* The Read Loop is executed 15 times */
389#define MAMR_RLFB_16X 0x00000000 /* The Read Loop is executed 16 times */
390#define MAMR_WLFB_MSK 0x000000f0 /* Write Loop Field B mask */
391#define MAMR_WLFB_1X 0x00000010 /* The Write Loop is executed 1 time */
392#define MAMR_WLFB_2X 0x00000020 /* The Write Loop is executed 2 times */
393#define MAMR_WLFB_3X 0x00000030 /* The Write Loop is executed 3 times */
394#define MAMR_WLFB_4X 0x00000040 /* The Write Loop is executed 4 times */
395#define MAMR_WLFB_5X 0x00000050 /* The Write Loop is executed 5 times */
396#define MAMR_WLFB_6X 0x00000060 /* The Write Loop is executed 6 times */
397#define MAMR_WLFB_7X 0x00000070 /* The Write Loop is executed 7 times */
398#define MAMR_WLFB_8X 0x00000080 /* The Write Loop is executed 8 times */
399#define MAMR_WLFB_9X 0x00000090 /* The Write Loop is executed 9 times */
400#define MAMR_WLFB_10X 0x000000a0 /* The Write Loop is executed 10 times */
401#define MAMR_WLFB_11X 0x000000b0 /* The Write Loop is executed 11 times */
402#define MAMR_WLFB_12X 0x000000c0 /* The Write Loop is executed 12 times */
403#define MAMR_WLFB_13X 0x000000d0 /* The Write Loop is executed 13 times */
404#define MAMR_WLFB_14X 0x000000e0 /* The Write Loop is executed 14 times */
405#define MAMR_WLFB_15X 0x000000f0 /* The Write Loop is executed 15 times */
406#define MAMR_WLFB_16X 0x00000000 /* The Write Loop is executed 16 times */
407#define MAMR_TLFB_MSK 0x0000000f /* Timer Loop Field B mask */
408#define MAMR_TLFB_1X 0x00000001 /* The Timer Loop is executed 1 time */
409#define MAMR_TLFB_2X 0x00000002 /* The Timer Loop is executed 2 times */
410#define MAMR_TLFB_3X 0x00000003 /* The Timer Loop is executed 3 times */
411#define MAMR_TLFB_4X 0x00000004 /* The Timer Loop is executed 4 times */
412#define MAMR_TLFB_5X 0x00000005 /* The Timer Loop is executed 5 times */
413#define MAMR_TLFB_6X 0x00000006 /* The Timer Loop is executed 6 times */
414#define MAMR_TLFB_7X 0x00000007 /* The Timer Loop is executed 7 times */
415#define MAMR_TLFB_8X 0x00000008 /* The Timer Loop is executed 8 times */
416#define MAMR_TLFB_9X 0x00000009 /* The Timer Loop is executed 9 times */
417#define MAMR_TLFB_10X 0x0000000a /* The Timer Loop is executed 10 times */
418#define MAMR_TLFB_11X 0x0000000b /* The Timer Loop is executed 11 times */
419#define MAMR_TLFB_12X 0x0000000c /* The Timer Loop is executed 12 times */
420#define MAMR_TLFB_13X 0x0000000d /* The Timer Loop is executed 13 times */
421#define MAMR_TLFB_14X 0x0000000e /* The Timer Loop is executed 14 times */
422#define MAMR_TLFB_15X 0x0000000f /* The Timer Loop is executed 15 times */
423#define MAMR_TLFB_16X 0x00000000 /* The Timer Loop is executed 16 times */
424
425/*-----------------------------------------------------------------------
426 * Timer Global Configuration Register 18-8
427 */
428#define TGCR_CAS4 0x8000 /* Cascade Timer 3 and 4 */
429#define TGCR_FRZ4 0x4000 /* Freeze timer 4 */
430#define TGCR_STP4 0x2000 /* Stop timer 4 */
431#define TGCR_RST4 0x1000 /* Reset timer 4 */
432#define TGCR_GM2 0x0800 /* Gate Mode for Pin 2 */
433#define TGCR_FRZ3 0x0400 /* Freeze timer 3 */
434#define TGCR_STP3 0x0200 /* Stop timer 3 */
435#define TGCR_RST3 0x0100 /* Reset timer 3 */
436#define TGCR_CAS2 0x0080 /* Cascade Timer 1 and 2 */
437#define TGCR_FRZ2 0x0040 /* Freeze timer 2 */
438#define TGCR_STP2 0x0020 /* Stop timer 2 */
439#define TGCR_RST2 0x0010 /* Reset timer 2 */
440#define TGCR_GM1 0x0008 /* Gate Mode for Pin 1 */
441#define TGCR_FRZ1 0x0004 /* Freeze timer 1 */
442#define TGCR_STP1 0x0002 /* Stop timer 1 */
443#define TGCR_RST1 0x0001 /* Reset timer 1 */
444
445
446/*-----------------------------------------------------------------------
447 * Timer Mode Register 18-9
448 */
449#define TMR_PS_MSK 0xff00 /* Prescaler Value */
450#define TMR_PS_SHIFT 8 /* Prescaler position */
451#define TMR_CE_MSK 0x00c0 /* Capture Edge and Enable Interrupt */
452#define TMR_CE_INTR_DIS 0x0000 /* Disable Interrupt on capture event */
453#define TMR_CE_RISING 0x0040 /* Capture on Rising TINx edge only */
454#define TMR_CE_FALLING 0x0080 /* Capture on Falling TINx edge only */
455#define TMR_CE_ANY 0x00c0 /* Capture on any TINx edge */
456#define TMR_OM 0x0020 /* Output Mode */
457#define TMR_ORI 0x0010 /* Output Reference Interrupt Enable */
458#define TMR_FRR 0x0008 /* Free Run/Restart */
459#define TMR_ICLK_MSK 0x0006 /* Timer Input Clock Source mask */
460#define TMR_ICLK_IN_CAS 0x0000 /* Internally cascaded input */
461#define TMR_ICLK_IN_GEN 0x0002 /* Internal General system clock */
462#define TMR_ICLK_IN_GEN_DIV16 0x0004 /* Internal General system clk div 16 */
463#define TMR_ICLK_TIN_PIN 0x0006 /* TINx pin */
464#define TMR_GE 0x0001 /* Gate Enable */
465
466
467/*-----------------------------------------------------------------------
468 * I2C Controller Registers
469 */
470#define I2MOD_REVD 0x20 /* Reverese Data */
471#define I2MOD_GCD 0x10 /* General Call Disable */
472#define I2MOD_FLT 0x08 /* Clock Filter */
473#define I2MOD_PDIV32 0x00 /* Pre-Divider 32 */
474#define I2MOD_PDIV16 0x02 /* Pre-Divider 16 */
475#define I2MOD_PDIV8 0x04 /* Pre-Divider 8 */
476#define I2MOD_PDIV4 0x06 /* Pre-Divider 4 */
477#define I2MOD_EN 0x01 /* Enable */
478
479#define I2CER_TXE 0x10 /* Tx Error */
480#define I2CER_BSY 0x04 /* Busy Condition */
481#define I2CER_TXB 0x02 /* Tx Buffer Transmitted */
482#define I2CER_RXB 0x01 /* Rx Buffer Received */
483#define I2CER_ALL (I2CER_TXE | I2CER_BSY | I2CER_TXB | I2CER_RXB)
484
485#define I2COM_STR 0x80 /* Start Transmit */
486#define I2COM_MASTER 0x01 /* Master mode */
487
488/*-----------------------------------------------------------------------
489 * SPI Controller Registers 31-10
490 */
491#define SPI_EMASK 0x37 /* Event Mask */
492#define SPI_MME 0x20 /* Multi-Master Error */
493#define SPI_TXE 0x10 /* Transmit Error */
494#define SPI_BSY 0x04 /* Busy */
495#define SPI_TXB 0x02 /* Tx Buffer Empty */
496#define SPI_RXB 0x01 /* RX Buffer full/closed */
497
498#define SPI_STR 0x80 /* SPCOM: Start transmit */
499
500/*-----------------------------------------------------------------------
501 * PCMCIA Interface General Control Register 17-12
502 */
503#define PCMCIA_GCRX_CXRESET 0x00000040
504#define PCMCIA_GCRX_CXOE 0x00000080
505
506#define PCMCIA_VS1(slot) (0x80000000 >> (slot << 4))
507#define PCMCIA_VS2(slot) (0x40000000 >> (slot << 4))
508#define PCMCIA_VS_MASK(slot) (0xc0000000 >> (slot << 4))
509#define PCMCIA_VS_SHIFT(slot) (30 - (slot << 4))
510
511#define PCMCIA_WP(slot) (0x20000000 >> (slot << 4))
512#define PCMCIA_CD2(slot) (0x10000000 >> (slot << 4))
513#define PCMCIA_CD1(slot) (0x08000000 >> (slot << 4))
514#define PCMCIA_BVD2(slot) (0x04000000 >> (slot << 4))
515#define PCMCIA_BVD1(slot) (0x02000000 >> (slot << 4))
516#define PCMCIA_RDY(slot) (0x01000000 >> (slot << 4))
517#define PCMCIA_RDY_L(slot) (0x00800000 >> (slot << 4))
518#define PCMCIA_RDY_H(slot) (0x00400000 >> (slot << 4))
519#define PCMCIA_RDY_R(slot) (0x00200000 >> (slot << 4))
520#define PCMCIA_RDY_F(slot) (0x00100000 >> (slot << 4))
521#define PCMCIA_MASK(slot) (0xFFFF0000 >> (slot << 4))
522
523/*-----------------------------------------------------------------------
524 * PCMCIA Option Register Definitions
525 *
526 * Bank Sizes:
527 */
528#define PCMCIA_BSIZE_1 0x00000000 /* Bank size: 1 Bytes */
529#define PCMCIA_BSIZE_2 0x08000000 /* Bank size: 2 Bytes */
530#define PCMCIA_BSIZE_4 0x18000000 /* Bank size: 4 Bytes */
531#define PCMCIA_BSIZE_8 0x10000000 /* Bank size: 8 Bytes */
532#define PCMCIA_BSIZE_16 0x30000000 /* Bank size: 16 Bytes */
533#define PCMCIA_BSIZE_32 0x38000000 /* Bank size: 32 Bytes */
534#define PCMCIA_BSIZE_64 0x28000000 /* Bank size: 64 Bytes */
535#define PCMCIA_BSIZE_128 0x20000000 /* Bank size: 128 Bytes */
536#define PCMCIA_BSIZE_256 0x60000000 /* Bank size: 256 Bytes */
537#define PCMCIA_BSIZE_512 0x68000000 /* Bank size: 512 Bytes */
538#define PCMCIA_BSIZE_1K 0x78000000 /* Bank size: 1 kB */
539#define PCMCIA_BSIZE_2K 0x70000000 /* Bank size: 2 kB */
540#define PCMCIA_BSIZE_4K 0x50000000 /* Bank size: 4 kB */
541#define PCMCIA_BSIZE_8K 0x58000000 /* Bank size: 8 kB */
542#define PCMCIA_BSIZE_16K 0x48000000 /* Bank size: 16 kB */
543#define PCMCIA_BSIZE_32K 0x40000000 /* Bank size: 32 kB */
544#define PCMCIA_BSIZE_64K 0xC0000000 /* Bank size: 64 kB */
545#define PCMCIA_BSIZE_128K 0xC8000000 /* Bank size: 128 kB */
546#define PCMCIA_BSIZE_256K 0xD8000000 /* Bank size: 256 kB */
547#define PCMCIA_BSIZE_512K 0xD0000000 /* Bank size: 512 kB */
548#define PCMCIA_BSIZE_1M 0xF0000000 /* Bank size: 1 MB */
549#define PCMCIA_BSIZE_2M 0xF8000000 /* Bank size: 2 MB */
550#define PCMCIA_BSIZE_4M 0xE8000000 /* Bank size: 4 MB */
551#define PCMCIA_BSIZE_8M 0xE0000000 /* Bank size: 8 MB */
552#define PCMCIA_BSIZE_16M 0xA0000000 /* Bank size: 16 MB */
553#define PCMCIA_BSIZE_32M 0xA8000000 /* Bank size: 32 MB */
554#define PCMCIA_BSIZE_64M 0xB8000000 /* Bank size: 64 MB */
555
556/* PCMCIA Timing */
557#define PCMCIA_SHT(t) ((t & 0x0F)<<16) /* Strobe Hold Time */
558#define PCMCIA_SST(t) ((t & 0x0F)<<12) /* Strobe Setup Time */
559#define PCMCIA_SL(t) ((t==32) ? 0 : ((t & 0x1F)<<7)) /* Strobe Length */
560
561/* PCMCIA Port Sizes */
562#define PCMCIA_PPS_8 0x00000000 /* 8 bit port size */
563#define PCMCIA_PPS_16 0x00000040 /* 16 bit port size */
564
565/* PCMCIA Region Select */
566#define PCMCIA_PRS_MEM 0x00000000 /* Common Memory Space */
567#define PCMCIA_PRS_ATTR 0x00000010 /* Attribute Space */
568#define PCMCIA_PRS_IO 0x00000018 /* I/O Space */
569#define PCMCIA_PRS_DMA 0x00000020 /* DMA, normal transfer */
570#define PCMCIA_PRS_DMA_LAST 0x00000028 /* DMA, last transactn */
571#define PCMCIA_PRS_CEx 0x00000030 /* A[22:23] ==> CE1,CE2 */
572
573#define PCMCIA_PSLOT_A 0x00000000 /* Slot A */
574#define PCMCIA_PSLOT_B 0x00000004 /* Slot B */
575#define PCMCIA_WPROT 0x00000002 /* Write Protect */
576#define PCMCIA_PV 0x00000001 /* Valid Bit */
577
578#define UPMA 0x00000000
579#define UPMB 0x00800000
580
581#endif /* __MPCXX_H__ */