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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 3d83c4a1d4dd7ea230d5b5c073e503dca883e409 / . / drivers / clk / sunxi / clk_a83t.c
blob: 36f7e14c45c3e061ac535f5b9c6d1b0da8ae874e [file] [log] [blame]
Jagan Teki03d87f52018-08-02 23:33:55 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
11#include <asm/arch/ccu.h>
12#include <dt-bindings/clock/sun8i-a83t-ccu.h>
13#include <dt-bindings/reset/sun8i-a83t-ccu.h>
14
15static struct ccu_clk_gate a83t_gates[] = {
Andre Przywarabb3e5aa2019-01-29 15:54:09 +0000[diff] [blame]16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
Jagan Teki82111462019-02-27 20:02:06 +0530[diff] [blame]19 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
20 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
Jagan Teki03d87f52018-08-02 23:33:55 +0530[diff] [blame]21 [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
22 [CLK_BUS_EHCI0] = GATE(0x060, BIT(26)),
23 [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)),
24 [CLK_BUS_OHCI0] = GATE(0x060, BIT(29)),
25
Jagan Teki4acc7112018-12-30 21:29:24 +0530[diff] [blame]26 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
27 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
28 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
29 [CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
30 [CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
31
Jagan Teki82111462019-02-27 20:02:06 +0530[diff] [blame]32 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
33 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
34
Jagan Teki03d87f52018-08-02 23:33:55 +0530[diff] [blame]35 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
36 [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
37 [CLK_USB_HSIC] = GATE(0x0cc, BIT(10)),
38 [CLK_USB_HSIC_12M] = GATE(0x0cc, BIT(11)),
39 [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
40};
41
42static struct ccu_reset a83t_resets[] = {
43 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
44 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
45 [RST_USB_HSIC] = RESET(0x0cc, BIT(2)),
46
Andre Przywarabb3e5aa2019-01-29 15:54:09 +0000[diff] [blame]47 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
48 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
49 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
Jagan Teki82111462019-02-27 20:02:06 +0530[diff] [blame]50 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
51 [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
Jagan Teki03d87f52018-08-02 23:33:55 +0530[diff] [blame]52 [RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
53 [RST_BUS_EHCI0] = RESET(0x2c0, BIT(26)),
54 [RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)),
55 [RST_BUS_OHCI0] = RESET(0x2c0, BIT(29)),
Jagan Teki8606f962018-12-30 21:37:31 +0530[diff] [blame]56
57 [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
58 [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
59 [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
60 [RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
61 [RST_BUS_UART4] = RESET(0x2d8, BIT(20)),
Jagan Teki03d87f52018-08-02 23:33:55 +0530[diff] [blame]62};
63
64static const struct ccu_desc a83t_ccu_desc = {
65 .gates = a83t_gates,
66 .resets = a83t_resets,
67};
68
69static int a83t_clk_bind(struct udevice *dev)
70{
71 return sunxi_reset_bind(dev, ARRAY_SIZE(a83t_resets));
72}
73
74static const struct udevice_id a83t_clk_ids[] = {
75 { .compatible = "allwinner,sun8i-a83t-ccu",
76 .data = (ulong)&a83t_ccu_desc },
77 { }
78};
79
80U_BOOT_DRIVER(clk_sun8i_a83t) = {
81 .name = "sun8i_a83t_ccu",
82 .id = UCLASS_CLK,
83 .of_match = a83t_clk_ids,
84 .priv_auto_alloc_size = sizeof(struct ccu_priv),
85 .ops = &sunxi_clk_ops,
86 .probe = sunxi_clk_probe,
87 .bind = a83t_clk_bind,
88};