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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 3d83c4a1d4dd7ea230d5b5c073e503dca883e409 / . / drivers / clk / sunxi / clk_r40.c
blob: 92907281f1ad746f3ede9f3b5a44859e449d3077 [file] [log] [blame]
Jagan Teki78eb2a42018-08-05 11:16:33 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
11#include <asm/arch/ccu.h>
12#include <dt-bindings/clock/sun8i-r40-ccu.h>
13#include <dt-bindings/reset/sun8i-r40-ccu.h>
14
15static struct ccu_clk_gate r40_gates[] = {
Andre Przywarabb3e5aa2019-01-29 15:54:09 +0000[diff] [blame]16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
19 [CLK_BUS_MMC3] = GATE(0x060, BIT(11)),
Jagan Teki82111462019-02-27 20:02:06 +0530[diff] [blame]20 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
21 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
22 [CLK_BUS_SPI2] = GATE(0x060, BIT(22)),
23 [CLK_BUS_SPI3] = GATE(0x060, BIT(23)),
Jagan Teki78eb2a42018-08-05 11:16:33 +0530[diff] [blame]24 [CLK_BUS_OTG] = GATE(0x060, BIT(25)),
25 [CLK_BUS_EHCI0] = GATE(0x060, BIT(26)),
26 [CLK_BUS_EHCI1] = GATE(0x060, BIT(27)),
27 [CLK_BUS_EHCI2] = GATE(0x060, BIT(28)),
28 [CLK_BUS_OHCI0] = GATE(0x060, BIT(29)),
29 [CLK_BUS_OHCI1] = GATE(0x060, BIT(30)),
30 [CLK_BUS_OHCI2] = GATE(0x060, BIT(31)),
31
Jagan Teki4acc7112018-12-30 21:29:24 +0530[diff] [blame]32 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
33 [CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
34 [CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
35 [CLK_BUS_UART3] = GATE(0x06c, BIT(19)),
36 [CLK_BUS_UART4] = GATE(0x06c, BIT(20)),
37 [CLK_BUS_UART5] = GATE(0x06c, BIT(21)),
38 [CLK_BUS_UART6] = GATE(0x06c, BIT(22)),
39 [CLK_BUS_UART7] = GATE(0x06c, BIT(23)),
40
Jagan Teki82111462019-02-27 20:02:06 +0530[diff] [blame]41 [CLK_SPI0] = GATE(0x0a0, BIT(31)),
42 [CLK_SPI1] = GATE(0x0a4, BIT(31)),
43 [CLK_SPI2] = GATE(0x0a8, BIT(31)),
44 [CLK_SPI3] = GATE(0x0ac, BIT(31)),
45
Jagan Teki78eb2a42018-08-05 11:16:33 +0530[diff] [blame]46 [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)),
47 [CLK_USB_PHY1] = GATE(0x0cc, BIT(9)),
48 [CLK_USB_PHY2] = GATE(0x0cc, BIT(10)),
49 [CLK_USB_OHCI0] = GATE(0x0cc, BIT(16)),
50 [CLK_USB_OHCI1] = GATE(0x0cc, BIT(17)),
51 [CLK_USB_OHCI2] = GATE(0x0cc, BIT(18)),
52};
53
54static struct ccu_reset r40_resets[] = {
55 [RST_USB_PHY0] = RESET(0x0cc, BIT(0)),
56 [RST_USB_PHY1] = RESET(0x0cc, BIT(1)),
57 [RST_USB_PHY2] = RESET(0x0cc, BIT(2)),
58
Andre Przywarabb3e5aa2019-01-29 15:54:09 +0000[diff] [blame]59 [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)),
60 [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)),
61 [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)),
62 [RST_BUS_MMC3] = RESET(0x2c0, BIT(11)),
Jagan Teki82111462019-02-27 20:02:06 +0530[diff] [blame]63 [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
64 [RST_BUS_SPI1] = RESET(0x2c0, BIT(21)),
65 [RST_BUS_SPI2] = RESET(0x2c0, BIT(22)),
66 [RST_BUS_SPI3] = RESET(0x2c0, BIT(23)),
Jagan Teki78eb2a42018-08-05 11:16:33 +0530[diff] [blame]67 [RST_BUS_OTG] = RESET(0x2c0, BIT(25)),
68 [RST_BUS_EHCI0] = RESET(0x2c0, BIT(26)),
69 [RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)),
70 [RST_BUS_EHCI2] = RESET(0x2c0, BIT(28)),
71 [RST_BUS_OHCI0] = RESET(0x2c0, BIT(29)),
72 [RST_BUS_OHCI1] = RESET(0x2c0, BIT(30)),
73 [RST_BUS_OHCI2] = RESET(0x2c0, BIT(31)),
Jagan Teki8606f962018-12-30 21:37:31 +0530[diff] [blame]74
75 [RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
76 [RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
77 [RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
78 [RST_BUS_UART3] = RESET(0x2d8, BIT(19)),
79 [RST_BUS_UART4] = RESET(0x2d8, BIT(20)),
80 [RST_BUS_UART5] = RESET(0x2d8, BIT(21)),
81 [RST_BUS_UART6] = RESET(0x2d8, BIT(22)),
82 [RST_BUS_UART7] = RESET(0x2d8, BIT(23)),
Jagan Teki78eb2a42018-08-05 11:16:33 +0530[diff] [blame]83};
84
85static const struct ccu_desc r40_ccu_desc = {
86 .gates = r40_gates,
87 .resets = r40_resets,
88};
89
90static int r40_clk_bind(struct udevice *dev)
91{
92 return sunxi_reset_bind(dev, ARRAY_SIZE(r40_resets));
93}
94
95static const struct udevice_id r40_clk_ids[] = {
96 { .compatible = "allwinner,sun8i-r40-ccu",
97 .data = (ulong)&r40_ccu_desc },
98 { }
99};
100
101U_BOOT_DRIVER(clk_sun8i_r40) = {
102 .name = "sun8i_r40_ccu",
103 .id = UCLASS_CLK,
104 .of_match = r40_clk_ids,
105 .priv_auto_alloc_size = sizeof(struct ccu_priv),
106 .ops = &sunxi_clk_ops,
107 .probe = sunxi_clk_probe,
108 .bind = r40_clk_bind,
109};