blob: bf6a614348354b4dac000308b782e45eaab82099 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Ulf Samuelssoncb82a532009-03-27 23:26:43 +01002/*
Andreas Bießmann99fa97e2010-10-18 22:58:29 +02003 * Copyright (C) 2010 Andreas Bießmann <biessmann.devel@googlemail.com>
4 *
5 * based on previous work by
6 *
Ulf Samuelssoncb82a532009-03-27 23:26:43 +01007 * Ulf Samuelsson <ulf@atmel.com>
8 * Rick Bronson <rick@efn.org>
9 *
10 * Configuration settings for the AT91RM9200EK board.
Ulf Samuelssoncb82a532009-03-27 23:26:43 +010011 */
12
Andreas Bießmann99fa97e2010-10-18 22:58:29 +020013#ifndef __AT91RM9200EK_CONFIG_H__
14#define __AT91RM9200EK_CONFIG_H__
Ulf Samuelssoncb82a532009-03-27 23:26:43 +010015
Alexey Brodkin1ace4022014-02-26 17:47:58 +040016#include <linux/sizes.h>
Jens Scharsig425de622010-02-03 22:45:42 +010017
Ulf Samuelssoncb82a532009-03-27 23:26:43 +010018/*
Andreas Bießmann3a4ff8b2010-11-30 09:45:03 +000019 * set some initial configurations depending on configure target
20 *
21 * at91rm9200ek_config -> boot from 0x0 in NOR Flash at CS0
22 * at91rm9200ek_ram_config -> continue booting from 0x20100000 in RAM; lowlevel
23 * initialisation was done by some preloader
24 */
25#ifdef CONFIG_RAMBOOT
26#define CONFIG_SKIP_LOWLEVEL_INIT
Andreas Bießmann3a4ff8b2010-11-30 09:45:03 +000027#endif
28
29/*
Andreas Bießmann99fa97e2010-10-18 22:58:29 +020030 * AT91C_XTAL_CLOCK is the frequency of external xtal in hertz
31 * AT91C_MAIN_CLOCK is the frequency of PLLA output
32 * AT91C_MASTER_CLOCK is the peripherial clock
33 * CONFIG_SYS_HZ_CLOCK is the value for CCR in tc0 (divider 2 is implicitely
34 * set in arch/arm/cpu/arm920t/at91/timer.c)
35 * CONFIG_SYS_HZ is the tick rate for timer tc0
Ulf Samuelssoncb82a532009-03-27 23:26:43 +010036 */
Andreas Bießmann99fa97e2010-10-18 22:58:29 +020037#define AT91C_XTAL_CLOCK 18432000
Andreas Bießmann6a372e92011-06-12 01:49:12 +000038#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
Andreas Bießmann99fa97e2010-10-18 22:58:29 +020039#define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39)
40#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3 )
41#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
Andreas Bießmann99fa97e2010-10-18 22:58:29 +020042
43/* CPU configuration */
Andreas Bießmann99fa97e2010-10-18 22:58:29 +020044#define CONFIG_AT91RM9200
45#define CONFIG_AT91RM9200EK
Andreas Bießmann99fa97e2010-10-18 22:58:29 +020046#define USE_920T_MMU
47
Andreas Bießmann6a372e92011-06-12 01:49:12 +000048#include <asm/hardware.h> /* needed for port definitions */
49
Andreas Bießmann99fa97e2010-10-18 22:58:29 +020050#define CONFIG_CMDLINE_TAG
51#define CONFIG_SETUP_MEMORY_TAGS
52#define CONFIG_INITRD_TAG
53
Ulf Samuelssoncb82a532009-03-27 23:26:43 +010054/*
Andreas Bießmann99fa97e2010-10-18 22:58:29 +020055 * Memory Configuration
Ulf Samuelssoncb82a532009-03-27 23:26:43 +010056 */
Andreas Bießmann99fa97e2010-10-18 22:58:29 +020057#define CONFIG_SYS_SDRAM_BASE 0x20000000
58#define CONFIG_SYS_SDRAM_SIZE SZ_32M
Ulf Samuelssoncb82a532009-03-27 23:26:43 +010059
Ulf Samuelssoncb82a532009-03-27 23:26:43 +010060/*
61 * LowLevel Init
62 */
63#ifndef CONFIG_SKIP_LOWLEVEL_INIT
Andreas Bießmann99fa97e2010-10-18 22:58:29 +020064#define CONFIG_SYS_USE_MAIN_OSCILLATOR
Ulf Samuelssoncb82a532009-03-27 23:26:43 +010065/* flash */
Ulf Samuelssoncb82a532009-03-27 23:26:43 +010066#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
67#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
68
69/* clocks */
70#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
71#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
72/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
73#define CONFIG_SYS_MCKR_VAL 0x00000202
74
75/* sdram */
76#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
77#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
78#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
79#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
80#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */
Andreas Bießmann99fa97e2010-10-18 22:58:29 +020081#define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */
Andreas Bießmann066df1a2010-12-04 11:31:46 +000082#define CONFIG_SYS_SDRAM1 (CONFIG_SYS_SDRAM_BASE+0x80)
Ulf Samuelssoncb82a532009-03-27 23:26:43 +010083#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
84#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
85#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
86#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
87#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
88#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
Ulf Samuelssoncb82a532009-03-27 23:26:43 +010089#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
90
Ulf Samuelssoncb82a532009-03-27 23:26:43 +010091/*
92 * Hardware drivers
93 */
Ulf Samuelssoncb82a532009-03-27 23:26:43 +010094/*
Andreas Bießmann99fa97e2010-10-18 22:58:29 +020095 * Choose a USART for serial console
96 * CONFIG_DBGU is DBGU unit on J10
97 * CONFIG_USART1 is USART1 on J14
Ulf Samuelssoncb82a532009-03-27 23:26:43 +010098 */
Andreas Bießmann3432a932011-06-12 01:49:14 +000099#define CONFIG_USART_BASE ATMEL_BASE_DBGU
100#define CONFIG_USART_ID 0/* ignored in arm */
Ulf Samuelssoncb82a532009-03-27 23:26:43 +0100101
Ulf Samuelssoncb82a532009-03-27 23:26:43 +0100102/*
Ulf Samuelssoncb82a532009-03-27 23:26:43 +0100103 * Network Driver Setting
104 */
Andreas Bießmann99fa97e2010-10-18 22:58:29 +0200105#define CONFIG_DRIVER_AT91EMAC
106#define CONFIG_SYS_RX_ETH_BUFFER 16
107#define CONFIG_RMII
Ulf Samuelssoncb82a532009-03-27 23:26:43 +0100108
109/*
110 * NOR Flash
111 */
Andreas Bießmann99fa97e2010-10-18 22:58:29 +0200112#define CONFIG_SYS_FLASH_BASE 0x10000000
113#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
114#define PHYS_FLASH_SIZE SZ_8M
115#define CONFIG_SYS_MAX_FLASH_BANKS 1
116#define CONFIG_SYS_MAX_FLASH_SECT 256
Ulf Samuelssoncb82a532009-03-27 23:26:43 +0100117
118/*
Andreas Bießmann3b835222010-10-18 22:58:31 +0200119 * USB Config
120 */
121#define CONFIG_USB_ATMEL 1
Bo Shendcd2f1a2013-10-21 16:14:00 +0800122#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
Andreas Bießmann3b835222010-10-18 22:58:31 +0200123#define CONFIG_USB_OHCI_NEW 1
Andreas Bießmann3b835222010-10-18 22:58:31 +0200124
125#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
Jens Scharsig80733992011-02-19 06:17:02 +0000126#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_USB_HOST_BASE
Andreas Bießmann3b835222010-10-18 22:58:31 +0200127#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200"
128#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
129
130/*
Ulf Samuelssoncb82a532009-03-27 23:26:43 +0100131 * Environment Settings
132 */
Ulf Samuelssoncb82a532009-03-27 23:26:43 +0100133
Ulf Samuelssoncb82a532009-03-27 23:26:43 +0100134/*
135 * after u-boot.bin
136 */
Markus Klotzbuechera9221f32019-05-15 15:15:54 +0200137
Ulf Samuelssoncb82a532009-03-27 23:26:43 +0100138/* The following #defines are needed to get flash environment right */
139#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
Andreas Bießmann99fa97e2010-10-18 22:58:29 +0200140#define CONFIG_SYS_MONITOR_LEN SZ_256K
Ulf Samuelssoncb82a532009-03-27 23:26:43 +0100141
142/*
143 * Boot option
144 */
Ulf Samuelssoncb82a532009-03-27 23:26:43 +0100145
Andreas Bießmann99fa97e2010-10-18 22:58:29 +0200146/* default load address */
147#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_16M
Ulf Samuelssoncb82a532009-03-27 23:26:43 +0100148
149/*
150 * Shell Settings
151 */
Ulf Samuelssoncb82a532009-03-27 23:26:43 +0100152
Ulf Samuelssoncb82a532009-03-27 23:26:43 +0100153/*
154 * Size of malloc() pool
155 */
Andreas Bießmann99fa97e2010-10-18 22:58:29 +0200156#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + SZ_128K, \
157 SZ_4K)
Ulf Samuelssoncb82a532009-03-27 23:26:43 +0100158
Andreas Bießmann99fa97e2010-10-18 22:58:29 +0200159#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200160 - GENERATED_GBL_DATA_SIZE)
Andreas Bießmann99fa97e2010-10-18 22:58:29 +0200161
Andreas Bießmann99fa97e2010-10-18 22:58:29 +0200162#endif /* __AT91RM9200EK_CONFIG_H__ */