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wdenke2211742002-11-02 23:30:20 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2002-2005
wdenke2211742002-11-02 23:30:20 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 *
26 * Configuration settings for the PCIPPC-2 board.
27 *
28 */
29
30/* ------------------------------------------------------------------------- */
31
32/*
33 * board/config.h - configuration options, board specific
34 */
35
36#ifndef __CONFIG_H
37#define __CONFIG_H
38
39/*
40 * High Level Configuration Options
41 * (easy to change)
42 */
43
44#define CONFIG_PCIPPC2 1 /* this is a PCIPPC2 board */
45
wdenkc837dcb2004-01-20 23:12:12 +000046#define CONFIG_BOARD_EARLY_INIT_F 1
wdenke2211742002-11-02 23:30:20 +000047#define CONFIG_MISC_INIT_R 1
48
49#define CONFIG_CONS_INDEX 1
50#define CONFIG_BAUDRATE 9600
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020051#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenke2211742002-11-02 23:30:20 +000052
wdenke2211742002-11-02 23:30:20 +000053#define CONFIG_PREBOOT ""
54#define CONFIG_BOOTDELAY 5
55
Jon Loeliger18225e82007-07-09 21:31:24 -050056/*
57 * BOOTP options
58 */
59#define CONFIG_BOOTP_SUBNETMASK
60#define CONFIG_BOOTP_GATEWAY
61#define CONFIG_BOOTP_HOSTNAME
62#define CONFIG_BOOTP_BOOTPATH
63#define CONFIG_BOOTP_BOOTFILESIZE
wdenke2211742002-11-02 23:30:20 +000064
65#define CONFIG_MAC_PARTITION
66#define CONFIG_DOS_PARTITION
67
Jon Loeligeracf02692007-07-08 14:49:44 -050068
69/*
70 * Command line configuration.
71 */
72#include <config_cmd_default.h>
73
74#define CONFIG_CMD_ASKENV
75#define CONFIG_CMD_BSP
76#define CONFIG_CMD_DATE
77#define CONFIG_CMD_DHCP
Jon Loeligeracf02692007-07-08 14:49:44 -050078#define CONFIG_CMD_ELF
79#define CONFIG_CMD_NFS
80#define CONFIG_CMD_PCI
81#define CONFIG_CMD_SNTP
wdenke2211742002-11-02 23:30:20 +000082
83#define CONFIG_PCI 1
84#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
85
wdenke2211742002-11-02 23:30:20 +000086/*
87 * Miscellaneous configurable options
88 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#define CONFIG_SYS_LONGHELP /* undef to save memory */
90#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenke2211742002-11-02 23:30:20 +000091
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
93#ifdef CONFIG_SYS_HUSH_PARSER
94#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenke2211742002-11-02 23:30:20 +000095#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +000097
98/* Print Buffer Size
99 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
wdenke2211742002-11-02 23:30:20 +0000101
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_MAXARGS 64 /* max number of command args */
103#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
104#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
wdenke2211742002-11-02 23:30:20 +0000105
106/*-----------------------------------------------------------------------
107 * Start addresses for the final memory configuration
108 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenke2211742002-11-02 23:30:20 +0000110 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_SDRAM_BASE 0x00000000
112#define CONFIG_SYS_FLASH_BASE 0xFFF00000
113#define CONFIG_SYS_FLASH_MAX_SIZE 0x00100000
wdenke2211742002-11-02 23:30:20 +0000114/* Maximum amount of RAM.
115 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 /* 512Mb */
wdenke2211742002-11-02 23:30:20 +0000117
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
wdenke2211742002-11-02 23:30:20 +0000119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
wdenke2211742002-11-02 23:30:20 +0000121
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
123#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenke2211742002-11-02 23:30:20 +0000124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_SDRAM_BASE && \
126 CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MAX_RAM_SIZE
127#define CONFIG_SYS_RAMBOOT
wdenke2211742002-11-02 23:30:20 +0000128#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#undef CONFIG_SYS_RAMBOOT
wdenke2211742002-11-02 23:30:20 +0000130#endif
131
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
133#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
wdenke2211742002-11-02 23:30:20 +0000134
135/*-----------------------------------------------------------------------
136 * Definitions for initial stack pointer and data area
137 */
138
139/* Size in bytes reserved for initial data
140 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_GBL_DATA_SIZE 128
wdenke2211742002-11-02 23:30:20 +0000142
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
144#define CONFIG_SYS_INIT_RAM_END 0x8000
145#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
146#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenke2211742002-11-02 23:30:20 +0000147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_INIT_RAM_LOCK
wdenke2211742002-11-02 23:30:20 +0000149
150/*
151 * Temporary buffer for serial data until the real serial driver
152 * is initialised (memtest will destroy this buffer)
153 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_SCONSOLE_ADDR CONFIG_SYS_INIT_RAM_ADDR
155#define CONFIG_SYS_SCONSOLE_SIZE 0x0002000
wdenke2211742002-11-02 23:30:20 +0000156
157/* SDRAM 0 - 256MB
158 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
160#define CONFIG_SYS_DBAT0U (CONFIG_SYS_SDRAM_BASE | \
wdenke2211742002-11-02 23:30:20 +0000161 BATU_BL_256M | BATU_VS | BATU_VP)
162/* SDRAM 1 - 256MB
163 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_DBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | \
wdenke2211742002-11-02 23:30:20 +0000165 BATL_PP_10 | BATL_MEMCOHERENCE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_DBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | \
wdenke2211742002-11-02 23:30:20 +0000167 BATU_BL_256M | BATU_VS | BATU_VP)
168
169/* Init RAM in the CPU DCache (no backing memory)
170 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_DBAT2L (CONFIG_SYS_INIT_RAM_ADDR | \
wdenke2211742002-11-02 23:30:20 +0000172 BATL_PP_10 | BATL_MEMCOHERENCE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_DBAT2U (CONFIG_SYS_INIT_RAM_ADDR | \
wdenke2211742002-11-02 23:30:20 +0000174 BATU_BL_128K | BATU_VS | BATU_VP)
175
176/* I/O and PCI memory at 0xf0000000
177 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_DBAT3L (0xf0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
179#define CONFIG_SYS_DBAT3U (0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
wdenke2211742002-11-02 23:30:20 +0000180
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_IBAT0L CONFIG_SYS_DBAT0L
182#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
183#define CONFIG_SYS_IBAT1L CONFIG_SYS_DBAT1L
184#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
185#define CONFIG_SYS_IBAT2L CONFIG_SYS_DBAT2L
186#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
187#define CONFIG_SYS_IBAT3L CONFIG_SYS_DBAT3L
188#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
wdenke2211742002-11-02 23:30:20 +0000189
190/*
191 * Low Level Configuration Settings
192 * (address mappings, register initial values, etc.)
193 * You should know what you are doing if you make changes here.
194 * For the detail description refer to the PCIPPC2 user's manual.
195 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_HZ 1000
197#define CONFIG_SYS_BUS_HZ 100000000 /* bus speed - 100 mhz */
198#define CONFIG_SYS_CPU_CLK 300000000
199#define CONFIG_SYS_BUS_CLK 100000000
wdenke2211742002-11-02 23:30:20 +0000200
201/*
202 * For booting Linux, the board info and command line data
203 * have to be in the first 8 MB of memory, since this is
204 * the maximum mapped by the Linux kernel during initialization.
205 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenke2211742002-11-02 23:30:20 +0000207
208/*-----------------------------------------------------------------------
209 * FLASH organization
210 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
212#define CONFIG_SYS_MAX_FLASH_SECT 16 /* Max number of sectors in one bank */
wdenke2211742002-11-02 23:30:20 +0000213
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
215#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
wdenke2211742002-11-02 23:30:20 +0000216
217/*
218 * Note: environment is not EMBEDDED in the U-Boot code.
219 * It's stored in flash separately.
220 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200221#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x70000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200223#define CONFIG_ENV_SIZE 0x1000 /* Size of the Environment */
224#define CONFIG_ENV_SECT_SIZE 0x10000 /* Size of the Environment Sector */
wdenke2211742002-11-02 23:30:20 +0000225
226/*-----------------------------------------------------------------------
227 * Cache Configuration
228 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_CACHELINE_SIZE 32
Jon Loeligeracf02692007-07-08 14:49:44 -0500230#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenke2211742002-11-02 23:30:20 +0000232#endif
233
234/*
235 * L2 cache
236 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#undef CONFIG_SYS_L2
wdenke2211742002-11-02 23:30:20 +0000238#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
wdenk8bde7f72003-06-27 21:31:46 +0000239 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
wdenke2211742002-11-02 23:30:20 +0000240#define L2_ENABLE (L2_INIT | L2CR_L2E)
241
242/*
243 * Internal Definitions
244 *
245 * Boot Flags
246 */
247#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
248#define BOOTFLAG_WARM 0x02 /* Software reboot */
249
250/*-----------------------------------------------------------------------
wdenke2211742002-11-02 23:30:20 +0000251 RTC m48t59
252*/
253#define CONFIG_RTC_MK48T59
254
255#define CONFIG_WATCHDOG
256
257#define CONFIG_NET_MULTI /* Multi ethernet cards support */
258
259#define CONFIG_EEPRO100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
wdenke2211742002-11-02 23:30:20 +0000261#define CONFIG_TULIP
262
263#endif /* __CONFIG_H */