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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Andy Fleming50586ef2008-10-30 16:47:16 -05002/*
3 * FSL SD/MMC Defines
4 *-------------------------------------------------------------------
5 *
Priyanka Jain32c8cfb2011-02-09 09:24:10 +05306 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc
Yangbo Luc927d652020-05-19 11:06:44 +08007 * Copyright 2020 NXP
Andy Fleming50586ef2008-10-30 16:47:16 -05008 */
9
10#ifndef __FSL_ESDHC_H__
11#define __FSL_ESDHC_H__
12
Masahiro Yamada1221ce42016-09-21 11:28:55 +090013#include <linux/errno.h>
Stefano Babicc67bee12010-02-05 15:11:27 +010014#include <asm/byteorder.h>
Anton Vorontsovb33433a2009-06-10 00:25:29 +040015
Pantelis Antoniou93bfd612014-03-11 19:34:20 +020016/* needed for the mmc_cfg definition */
17#include <mmc.h>
18
Andy Fleming50586ef2008-10-30 16:47:16 -050019/* FSL eSDHC-specific constants */
20#define SYSCTL 0x0002e02c
21#define SYSCTL_INITA 0x08000000
22#define SYSCTL_TIMEOUT_MASK 0x000f0000
Li Yang1118cdb2010-01-07 16:00:13 +080023#define SYSCTL_CLOCK_MASK 0x0000fff0
Stefano Babicc67bee12010-02-05 15:11:27 +010024#define SYSCTL_CKEN 0x00000008
Andy Fleming50586ef2008-10-30 16:47:16 -050025#define SYSCTL_PEREN 0x00000004
26#define SYSCTL_HCKEN 0x00000002
27#define SYSCTL_IPGEN 0x00000001
Jerry Huang48bb3bb2010-03-18 15:57:06 -050028#define SYSCTL_RSTA 0x01000000
Dirk Behme7a5b8022012-03-26 03:13:05 +000029#define SYSCTL_RSTC 0x02000000
30#define SYSCTL_RSTD 0x04000000
Andy Fleming50586ef2008-10-30 16:47:16 -050031
32#define IRQSTAT 0x0002e030
33#define IRQSTAT_DMAE (0x10000000)
34#define IRQSTAT_AC12E (0x01000000)
35#define IRQSTAT_DEBE (0x00400000)
36#define IRQSTAT_DCE (0x00200000)
37#define IRQSTAT_DTOE (0x00100000)
38#define IRQSTAT_CIE (0x00080000)
39#define IRQSTAT_CEBE (0x00040000)
40#define IRQSTAT_CCE (0x00020000)
41#define IRQSTAT_CTOE (0x00010000)
42#define IRQSTAT_CINT (0x00000100)
43#define IRQSTAT_CRM (0x00000080)
44#define IRQSTAT_CINS (0x00000040)
45#define IRQSTAT_BRR (0x00000020)
46#define IRQSTAT_BWR (0x00000010)
47#define IRQSTAT_DINT (0x00000008)
48#define IRQSTAT_BGE (0x00000004)
49#define IRQSTAT_TC (0x00000002)
50#define IRQSTAT_CC (0x00000001)
51
52#define CMD_ERR (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE)
Andrew Gabbasov9b74dc52013-04-07 23:06:08 +000053#define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE | \
54 IRQSTAT_DMAE)
55#define DATA_COMPLETE (IRQSTAT_TC | IRQSTAT_DINT)
Andy Fleming50586ef2008-10-30 16:47:16 -050056
57#define IRQSTATEN 0x0002e034
58#define IRQSTATEN_DMAE (0x10000000)
59#define IRQSTATEN_AC12E (0x01000000)
60#define IRQSTATEN_DEBE (0x00400000)
61#define IRQSTATEN_DCE (0x00200000)
62#define IRQSTATEN_DTOE (0x00100000)
63#define IRQSTATEN_CIE (0x00080000)
64#define IRQSTATEN_CEBE (0x00040000)
65#define IRQSTATEN_CCE (0x00020000)
66#define IRQSTATEN_CTOE (0x00010000)
67#define IRQSTATEN_CINT (0x00000100)
68#define IRQSTATEN_CRM (0x00000080)
69#define IRQSTATEN_CINS (0x00000040)
70#define IRQSTATEN_BRR (0x00000020)
71#define IRQSTATEN_BWR (0x00000010)
72#define IRQSTATEN_DINT (0x00000008)
73#define IRQSTATEN_BGE (0x00000004)
74#define IRQSTATEN_TC (0x00000002)
75#define IRQSTATEN_CC (0x00000001)
76
Yangbo Lub1a42472020-09-01 16:58:01 +080077/* eSDHC control register */
Yangbo Lu2d9ca2c2015-04-22 13:57:40 +080078#define ESDHCCTL 0x0002e40c
79#define ESDHCCTL_PCS (0x00080000)
Yangbo Lub1a42472020-09-01 16:58:01 +080080#define ESDHCCTL_FAF (0x00040000)
Yangbo Lu2d9ca2c2015-04-22 13:57:40 +080081
Andy Fleming50586ef2008-10-30 16:47:16 -050082#define PRSSTAT 0x0002e024
Dirk Behme7a5b8022012-03-26 03:13:05 +000083#define PRSSTAT_DAT0 (0x01000000)
Andy Fleming50586ef2008-10-30 16:47:16 -050084#define PRSSTAT_CLSL (0x00800000)
85#define PRSSTAT_WPSPL (0x00080000)
86#define PRSSTAT_CDPL (0x00040000)
87#define PRSSTAT_CINS (0x00010000)
88#define PRSSTAT_BREN (0x00000800)
Dipen Dudhat77c14582009-10-05 15:41:58 +053089#define PRSSTAT_BWEN (0x00000400)
Yangbo Lu2d9ca2c2015-04-22 13:57:40 +080090#define PRSSTAT_SDSTB (0X00000008)
Andy Fleming50586ef2008-10-30 16:47:16 -050091#define PRSSTAT_DLA (0x00000004)
92#define PRSSTAT_CICHB (0x00000002)
93#define PRSSTAT_CIDHB (0x00000001)
94
95#define PROCTL 0x0002e028
96#define PROCTL_INIT 0x00000020
97#define PROCTL_DTW_4 0x00000002
98#define PROCTL_DTW_8 0x00000004
Angelo Dureghello1f15cb82019-01-19 10:40:38 +010099#define PROCTL_D3CD 0x00000008
Michael Walle361a4222020-10-12 10:07:14 +0200100#define PROCTL_DMAS_MASK 0x00000300
101#define PROCTL_DMAS_SDMA 0x00000000
102#define PROCTL_DMAS_ADMA1 0x00000100
103#define PROCTL_DMAS_ADMA2 0x00000300
Yangbo Luc927d652020-05-19 11:06:44 +0800104#define PROCTL_VOLT_SEL 0x00000400
Andy Fleming50586ef2008-10-30 16:47:16 -0500105
106#define CMDARG 0x0002e008
107
108#define XFERTYP 0x0002e00c
109#define XFERTYP_CMD(x) ((x & 0x3f) << 24)
110#define XFERTYP_CMDTYP_NORMAL 0x0
111#define XFERTYP_CMDTYP_SUSPEND 0x00400000
112#define XFERTYP_CMDTYP_RESUME 0x00800000
113#define XFERTYP_CMDTYP_ABORT 0x00c00000
114#define XFERTYP_DPSEL 0x00200000
115#define XFERTYP_CICEN 0x00100000
116#define XFERTYP_CCCEN 0x00080000
117#define XFERTYP_RSPTYP_NONE 0
118#define XFERTYP_RSPTYP_136 0x00010000
119#define XFERTYP_RSPTYP_48 0x00020000
120#define XFERTYP_RSPTYP_48_BUSY 0x00030000
121#define XFERTYP_MSBSEL 0x00000020
122#define XFERTYP_DTDSEL 0x00000010
Volodymyr Riazantsev0e1bf612015-01-20 10:16:44 -0500123#define XFERTYP_DDREN 0x00000008
Andy Fleming50586ef2008-10-30 16:47:16 -0500124#define XFERTYP_AC12EN 0x00000004
125#define XFERTYP_BCEN 0x00000002
126#define XFERTYP_DMAEN 0x00000001
127
128#define CINS_TIMEOUT 1000
Benoît Thébaudeaubcfb3652017-10-29 22:08:58 +0100129#define PIO_TIMEOUT 500
Andy Fleming50586ef2008-10-30 16:47:16 -0500130
131#define DSADDR 0x2e004
132
133#define CMDRSP0 0x2e010
134#define CMDRSP1 0x2e014
135#define CMDRSP2 0x2e018
136#define CMDRSP3 0x2e01c
137
138#define DATPORT 0x2e020
139
140#define WML 0x2e044
141#define WML_WRITE 0x00010000
Priyanka Jain32c8cfb2011-02-09 09:24:10 +0530142#ifdef CONFIG_FSL_SDHC_V2_3
143#define WML_RD_WML_MAX 0x80
144#define WML_WR_WML_MAX 0x80
145#define WML_RD_WML_MAX_VAL 0x0
146#define WML_WR_WML_MAX_VAL 0x0
147#define WML_RD_WML_MASK 0x7f
148#define WML_WR_WML_MASK 0x7f0000
149#else
150#define WML_RD_WML_MAX 0x10
151#define WML_WR_WML_MAX 0x80
152#define WML_RD_WML_MAX_VAL 0x10
153#define WML_WR_WML_MAX_VAL 0x80
Roy Zangab467c52010-02-09 18:23:33 +0800154#define WML_RD_WML_MASK 0xff
155#define WML_WR_WML_MASK 0xff0000
Priyanka Jain32c8cfb2011-02-09 09:24:10 +0530156#endif
Andy Fleming50586ef2008-10-30 16:47:16 -0500157
158#define BLKATTR 0x2e004
159#define BLKATTR_CNT(x) ((x & 0xffff) << 16)
160#define BLKATTR_SIZE(x) (x & 0x1fff)
161#define MAX_BLK_CNT 0x7fff /* so malloc will have enough room with 32M */
162
Yangbo Lub1a42472020-09-01 16:58:01 +0800163/* Auto CMD error status register / system control 2 register */
164#define EXECUTE_TUNING 0x00400000
165#define SMPCLKSEL 0x00800000
166#define UHSM_MASK 0x00070000
167#define UHSM_SDR104_HS200 0x00030000
168
Yangbo Lu5b05fc02019-10-31 18:54:21 +0800169/* Host controller capabilities register */
170#define HOSTCAPBLT_VS18 0x04000000
171#define HOSTCAPBLT_VS30 0x02000000
172#define HOSTCAPBLT_VS33 0x01000000
173#define HOSTCAPBLT_SRS 0x00800000
174#define HOSTCAPBLT_DMAS 0x00400000
175#define HOSTCAPBLT_HSS 0x00200000
Andy Fleming50586ef2008-10-30 16:47:16 -0500176
Yangbo Lub1a42472020-09-01 16:58:01 +0800177/* Tuning block control register */
178#define TBCTL_TB_EN 0x00000004
Yangbo Ludb8f9362020-09-01 16:58:05 +0800179#define HS400_MODE 0x00000010
180#define HS400_WNDW_ADJUST 0x00000040
181
182/* SD clock control register */
183#define CMD_CLK_CTL 0x00008000
184
185/* SD timing control register */
186#define FLW_CTL_BG 0x00008000
187
188/* DLL config 0 register */
189#define DLL_ENABLE 0x80000000
Yangbo Lu8ee802f2020-10-20 11:04:52 +0800190#define DLL_RESET 0x40000000
Yangbo Ludb8f9362020-09-01 16:58:05 +0800191#define DLL_FREQ_SEL 0x08000000
Yangbo Lub1a42472020-09-01 16:58:01 +0800192
Michael Walled3b745f2021-03-17 15:01:37 +0100193/* DLL config 1 register */
194#define DLL_PD_PULSE_STRETCH_SEL 0x80000000
195
Yangbo Lu8ee802f2020-10-20 11:04:52 +0800196/* DLL status 0 register */
197#define DLL_STS_SLV_LOCK 0x08000000
198
Yangbo Lub1a42472020-09-01 16:58:01 +0800199#define MAX_TUNING_LOOP 40
200
Michael Walle361a4222020-10-12 10:07:14 +0200201#define HOSTVER_VENDOR(x) (((x) >> 8) & 0xff)
202#define VENDOR_V_10 0x00
203#define VENDOR_V_20 0x10
204#define VENDOR_V_21 0x11
205#define VENDOR_V_22 0x12
206#define VENDOR_V_23 0x13
207#define VENDOR_V_30 0x20
208#define VENDOR_V_31 0x21
209#define VENDOR_V_32 0x22
210
Stefano Babicc67bee12010-02-05 15:11:27 +0100211struct fsl_esdhc_cfg {
Peng Fan5330c7d2016-03-15 17:57:50 +0800212 phys_addr_t esdhc_base;
Benoît Thébaudeaua2ac1b32012-10-01 08:36:25 +0000213 u32 sdhc_clk;
Abbas Razaaad46592013-03-25 09:13:34 +0000214 u8 max_bus_width;
Peng Fan32a91792017-06-12 17:50:53 +0800215 int vs18_enable; /* Use 1.8V if set to 1 */
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200216 struct mmc_config cfg;
Stefano Babicc67bee12010-02-05 15:11:27 +0100217};
218
219/* Select the correct accessors depending on endianess */
Wang Huanc82e9de2014-09-05 13:52:39 +0800220#if defined CONFIG_SYS_FSL_ESDHC_LE
221#define esdhc_read32 in_le32
222#define esdhc_write32 out_le32
223#define esdhc_clrsetbits32 clrsetbits_le32
224#define esdhc_clrbits32 clrbits_le32
225#define esdhc_setbits32 setbits_le32
226#elif defined(CONFIG_SYS_FSL_ESDHC_BE)
227#define esdhc_read32 in_be32
228#define esdhc_write32 out_be32
229#define esdhc_clrsetbits32 clrsetbits_be32
230#define esdhc_clrbits32 clrbits_be32
231#define esdhc_setbits32 setbits_be32
232#elif __BYTE_ORDER == __LITTLE_ENDIAN
Stefano Babicc67bee12010-02-05 15:11:27 +0100233#define esdhc_read32 in_le32
234#define esdhc_write32 out_le32
235#define esdhc_clrsetbits32 clrsetbits_le32
236#define esdhc_clrbits32 clrbits_le32
237#define esdhc_setbits32 setbits_le32
238#elif __BYTE_ORDER == __BIG_ENDIAN
239#define esdhc_read32 in_be32
240#define esdhc_write32 out_be32
241#define esdhc_clrsetbits32 clrsetbits_be32
242#define esdhc_clrbits32 clrbits_be32
243#define esdhc_setbits32 setbits_be32
244#else
245#error "Endianess is not defined: please fix to continue"
246#endif
247
Anton Vorontsovb33433a2009-06-10 00:25:29 +0400248#ifdef CONFIG_FSL_ESDHC
Masahiro Yamadab75d8dc2020-06-26 15:13:33 +0900249int fsl_esdhc_mmc_init(struct bd_info *bis);
250int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg);
251void fdt_fixup_esdhc(void *blob, struct bd_info *bd);
Anton Vorontsovb33433a2009-06-10 00:25:29 +0400252#else
Masahiro Yamadab75d8dc2020-06-26 15:13:33 +0900253static inline int fsl_esdhc_mmc_init(struct bd_info *bis) { return -ENOSYS; }
254static inline void fdt_fixup_esdhc(void *blob, struct bd_info *bd) {}
Anton Vorontsovb33433a2009-06-10 00:25:29 +0400255#endif /* CONFIG_FSL_ESDHC */
Ying Zhangbb0dc102013-08-16 15:16:11 +0800256void __noreturn mmc_boot(void);
Prabhakar Kushwaha1eaa7422014-04-08 19:13:22 +0530257void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst);
Andy Fleming50586ef2008-10-30 16:47:16 -0500258
259#endif /* __FSL_ESDHC_H__ */