blob: 62fe97e76ac02c19a457ac55d770516c1e46c0aa [file] [log] [blame]
wdenk81a88242002-10-26 15:22:42 +00001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
Detlev Zundel792a09e2009-05-13 10:54:10 +02005 * Gary Jennejohn <garyj@denx.de>
wdenk81a88242002-10-26 15:22:42 +00006 * David Mueller <d.mueller@elsoft.ch>
7 *
8 * Configuation settings for the SAMSUNG SMDK2410 board.
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
32/*
wdenk81a88242002-10-26 15:22:42 +000033 * High Level Configuration Options
34 * (easy to change)
35 */
kevin.morfitt@fearnside-systems.co.ukac678042009-11-17 18:30:34 +090036#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
37#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */
38#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */
39#define CONFIG_SMDK2410 1 /* on a SAMSUNG SMDK2410 Board */
wdenk81a88242002-10-26 15:22:42 +000040
41/* input clock of PLL */
wdenk7f6c2cb2002-11-10 22:06:23 +000042#define CONFIG_SYS_CLK_FREQ 12000000/* the SMDK2410 has 12MHz input clock */
wdenk81a88242002-10-26 15:22:42 +000043
44
45#define USE_920T_MMU 1
46#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
47
48/*
49 * Size of malloc() pool
50 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020051#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
wdenk81a88242002-10-26 15:22:42 +000052
53/*
54 * Hardware drivers
55 */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -070056#define CONFIG_NET_MULTI
57#define CONFIG_CS8900 /* we have a CS8900 on-board */
58#define CONFIG_CS8900_BASE 0x19000300
59#define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */
wdenk81a88242002-10-26 15:22:42 +000060
61/*
62 * select serial console configuration
63 */
Jean-Christophe PLAGNIOL-VILLARD300f99f2009-03-30 18:58:39 +020064#define CONFIG_S3C24X0_SERIAL
wdenk81a88242002-10-26 15:22:42 +000065#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK2410 */
66
wdenk48b42612003-06-19 23:01:32 +000067/************************************************************
68 * RTC
69 ************************************************************/
70#define CONFIG_RTC_S3C24X0 1
71
wdenk81a88242002-10-26 15:22:42 +000072/* allow to overwrite serial and ethaddr */
73#define CONFIG_ENV_OVERWRITE
74
75#define CONFIG_BAUDRATE 115200
76
wdenk81a88242002-10-26 15:22:42 +000077
Jon Loeliger46da1e92007-07-04 22:33:30 -050078/*
Jon Loeliger079a1362007-07-10 10:12:10 -050079 * BOOTP options
80 */
81#define CONFIG_BOOTP_BOOTFILESIZE
82#define CONFIG_BOOTP_BOOTPATH
83#define CONFIG_BOOTP_GATEWAY
84#define CONFIG_BOOTP_HOSTNAME
85
86
87/*
Jon Loeliger46da1e92007-07-04 22:33:30 -050088 * Command line configuration.
89 */
90#include <config_cmd_default.h>
91
92#define CONFIG_CMD_CACHE
Jon Loeliger46da1e92007-07-04 22:33:30 -050093#define CONFIG_CMD_DATE
94#define CONFIG_CMD_ELF
95
wdenk81a88242002-10-26 15:22:42 +000096
97#define CONFIG_BOOTDELAY 3
Wolfgang Denk53677ef2008-05-20 16:00:29 +020098/*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */
wdenk81a88242002-10-26 15:22:42 +000099/*#define CONFIG_ETHADDR 08:00:3e:26:0a:5b */
100#define CONFIG_NETMASK 255.255.255.0
101#define CONFIG_IPADDR 10.0.0.110
102#define CONFIG_SERVERIP 10.0.0.1
103/*#define CONFIG_BOOTFILE "elinos-lart" */
104/*#define CONFIG_BOOTCOMMAND "tftp; bootm" */
105
Jon Loeliger46da1e92007-07-04 22:33:30 -0500106#if defined(CONFIG_CMD_KGDB)
wdenk81a88242002-10-26 15:22:42 +0000107#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
108/* what's this ? it's not used anywhere */
109#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
110#endif
111
112/*
113 * Miscellaneous configurable options
114 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_LONGHELP /* undef to save memory */
116#define CONFIG_SYS_PROMPT "SMDK2410 # " /* Monitor Command Prompt */
117#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
118#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
119#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
120#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk81a88242002-10-26 15:22:42 +0000121
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */
123#define CONFIG_SYS_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
wdenk81a88242002-10-26 15:22:42 +0000124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_LOAD_ADDR 0x33000000 /* default load address */
wdenk81a88242002-10-26 15:22:42 +0000126
kevin.morfitt@fearnside-systems.co.ukcd856622009-09-06 00:33:13 +0900127#define CONFIG_SYS_HZ 1000
wdenk81a88242002-10-26 15:22:42 +0000128
129/* valid baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk81a88242002-10-26 15:22:42 +0000131
132/*-----------------------------------------------------------------------
133 * Stack sizes
134 *
135 * The stack sizes are set up in start.S using the settings below
136 */
137#define CONFIG_STACKSIZE (128*1024) /* regular stack */
138#ifdef CONFIG_USE_IRQ
139#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
140#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
141#endif
142
143/*-----------------------------------------------------------------------
144 * Physical Memory Map
145 */
146#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
147#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
148#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
149
150#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
151
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
wdenk81a88242002-10-26 15:22:42 +0000153
154/*-----------------------------------------------------------------------
155 * FLASH and environment organization
156 */
157
158#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */
159#if 0
160#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */
161#endif
162
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
wdenk81a88242002-10-26 15:22:42 +0000164#ifdef CONFIG_AMD_LV800
165#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_MAX_FLASH_SECT (19) /* max number of sectors on one chip */
167#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */
wdenk81a88242002-10-26 15:22:42 +0000168#endif
169#ifdef CONFIG_AMD_LV400
170#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_MAX_FLASH_SECT (11) /* max number of sectors on one chip */
172#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */
wdenk81a88242002-10-26 15:22:42 +0000173#endif
174
175/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_FLASH_ERASE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
177#define CONFIG_SYS_FLASH_WRITE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenk81a88242002-10-26 15:22:42 +0000178
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200179#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200180#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
wdenk81a88242002-10-26 15:22:42 +0000181
182#endif /* __CONFIG_H */