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Lukasz Majewski548cc102018-12-05 17:04:02 +01001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * ddrmc DDR3 calibration code for NXP's VF610
4 *
5 * Copyright (C) 2018 DENX Software Engineering
6 * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
7 *
8 */
9
10#ifndef __DDRMC_VF610_CALIBRATOIN_H_
11#define __DDRMC_VF610_CALIBRATOIN_H_
12
13/*
14 * Number of "samples" in the calibration bitmap
15 * to be considered during calibration.
16 */
17#define N_SAMPLES 3
18
19/*
20 * Constants to indicate if we are looking for a rising or
21 * falling edge in the calibration bitmap
22 */
23enum edge {
24 FALLING_EDGE = 1,
25 RISING_EDGE
26};
27
28/*
29 * The max number of delay elements when DQS to DQ setting
30 */
31#define DDRMC_DQS_DQ_MAX_DELAY 0xFF
32
33/**
34 * ddrmc_calibration - Vybrid's (VF610) DDR3 calibration code
35 *
36 * This function is calculating proper memory controller values
37 * during run time.
38 *
39 * @param ddrmr_regs - memory controller registers
40 *
Heinrich Schuchardt185f8122022-01-19 18:05:50 +010041 * Return: 0 on success, otherwise error code
Lukasz Majewski548cc102018-12-05 17:04:02 +010042 */
43int ddrmc_calibration(struct ddrmr_regs *ddrmr);
44
45#endif /* __DDRMC_VF610_CALIBRATOIN_H_ */