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wdenk281e00a2004-08-01 22:48:16 +00001/*
2 * Copyright (C) 2004 Sascha Hauer, Pengutronix
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of
7 * the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
17 * MA 02111-1307 USA
18 */
19
20#ifndef __CONFIG_H
21#define __CONFIG_H
22
23#define CONFIG_ARM920T 1 /* this is an ARM920T CPU */
24#define CONFIG_IMX 1 /* in a Motorola MC9328MXL Chip */
25#define CONFIG_MX1FS2 1 /* on a mx1fs2 board */
26#undef CONFIG_USE_IRQ /* don't need use IRQ/FIQ */
27
28/*
29 * Select serial console configuration
30 */
31#undef _CONFIG_UART1 /* internal uart 1 */
32#define _CONFIG_UART2 /* internal uart 2 */
33#undef _CONFIG_UART3 /* internal uart 3 */
34#undef _CONFIG_UART4 /* internal uart 4 */
35#undef CONFIG_SILENT_CONSOLE /* use this to disable output */
36
Jon Loeliger5dc11a52007-07-04 22:33:01 -050037/*
Jon Loeliger7f5c0152007-07-10 09:38:02 -050038 * BOOTP options
39 */
40#define CONFIG_BOOTP_BOOTFILESIZE
41#define CONFIG_BOOTP_BOOTPATH
42#define CONFIG_BOOTP_GATEWAY
43#define CONFIG_BOOTP_HOSTNAME
44
Jon Loeliger7f5c0152007-07-10 09:38:02 -050045/*
Jon Loeliger5dc11a52007-07-04 22:33:01 -050046 * Command line configuration.
47 */
48#include <config_cmd_default.h>
49
50#define CONFIG_CMD_JFFS2
51
Jon Loeliger5dc11a52007-07-04 22:33:01 -050052#undef CONFIG_CMD_CONSOLE
Wolfgang Denk74de7ae2009-04-01 23:34:12 +020053#undef CONFIG_CMD_DHCP
54#undef CONFIG_CMD_LOADS
Jon Loeliger5dc11a52007-07-04 22:33:01 -050055#undef CONFIG_CMD_NET
56#undef CONFIG_CMD_PING
Wolfgang Denk74de7ae2009-04-01 23:34:12 +020057#undef CONFIG_CMD_SOURCE
Jon Loeliger5dc11a52007-07-04 22:33:01 -050058
wdenk281e00a2004-08-01 22:48:16 +000059/*
60 * Boot options. Setting delay to -1 stops autostart count down.
61 */
62#define CONFIG_BOOTDELAY 10
63#define CONFIG_BOOTARGS "root=/dev/mtdblock4 console=ttySMX0,115200n8 rootfstype=jffs2"
64#define CONFIG_BOOTCOMMAND "bootm 10080000"
65#define CONFIG_SHOW_BOOT_PROGRESS
66
67/*
68 * General options for u-boot. Modify to save memory foot print
69 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070#define CONFIG_SYS_LONGHELP /* undef saves memory */
71#define CONFIG_SYS_PROMPT "mx1fs2> " /* prompt string */
72#define CONFIG_SYS_CBSIZE 256 /* console I/O buffer */
73#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* print buffer size */
74#define CONFIG_SYS_MAXARGS 16 /* max command args */
75#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot args buf size */
wdenk281e00a2004-08-01 22:48:16 +000076
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_SYS_MEMTEST_START 0x08100000 /* memtest test area */
78#define CONFIG_SYS_MEMTEST_END 0x08F00000
wdenk281e00a2004-08-01 22:48:16 +000079
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */
81#define CONFIG_SYS_CPUSPEED 0x141 /* core clock - register value */
wdenk281e00a2004-08-01 22:48:16 +000082
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk281e00a2004-08-01 22:48:16 +000084#define CONFIG_BAUDRATE 115200
85/*
86 * Definitions related to passing arguments to kernel.
87 */
88#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */
89#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */
90#define CONFIG_INITRD_TAG 1 /* send initrd params */
91#undef CONFIG_VFD /* do not send framebuffer setup */
92
wdenk281e00a2004-08-01 22:48:16 +000093/*
94 * Malloc pool need to host env + 128 Kb reserve for other allocations.
95 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128<<10) )
wdenk281e00a2004-08-01 22:48:16 +000097
wdenk281e00a2004-08-01 22:48:16 +000098#define CONFIG_STACKSIZE (120<<10) /* stack size */
99
100#ifdef CONFIG_USE_IRQ
101#define CONFIG_STACKSIZE_IRQ (4<<10) /* IRQ stack */
102#define CONFIG_STACKSIZE_FIQ (4<<10) /* FIQ stack */
103#endif
104
105/* SDRAM Setup Values
106 * 0x910a8300 Precharge Command CAS 3
107 * 0x910a8200 Precharge Command CAS 2
108 *
109 * 0xa10a8300 AutoRefresh Command CAS 3
110 * 0xa10a8200 Set AutoRefresh Command CAS 2
111 */
112#define PRECHARGE_CMD 0x910a8300
113#define AUTOREFRESH_CMD 0xa10a8300
114
wdenk281e00a2004-08-01 22:48:16 +0000115#define BUS32BIT_VERSION
116/*
117 * SDRAM Memory Map
118 */
119#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */
120#define MX1FS2_SDRAM_1 0x08000000 /* SDRAM bank #1 */
121#ifdef BUS32BIT_VERSION
122#define MX1FS2_SDRAM_1_SIZE (0x04000000 - 0x100000) /* 64 MB - 1M Framebuffer */
123#else
124#define MX1FS2_SDRAM_1_SIZE (0x01FC0000 - 0x100000) /* 32 MB - 1M Framebuffer */
125#endif
126/*
127 * Flash Controller settings
128 */
129
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* FLASH banks count (not chip count)*/
131#define CONFIG_SYS_MAX_FLASH_SECT 256 /* number of sector in FLASH bank */
wdenk281e00a2004-08-01 22:48:16 +0000132
133#ifdef BUS32BIT_VERSION
134#define MX1FS2_FLASH_BUS_WIDTH 4 /* we use 32 bit FLASH memory... */
135#define MX1FS2_FLASH_INTERLEAVE 2 /* ... made of 2 chips */
136#define MX1FS2_FLASH_BANK_SIZE 0x02000000 /* size of one flash bank*/
137#define MX1FS2_FLASH_SECT_SIZE 0x00020000 /* size of erase sector */
wdenk281e00a2004-08-01 22:48:16 +0000138#else
139#define MX1FS2_FLASH_BUS_WIDTH 2 /* we use 16 bit FLASH memory... */
140#define MX1FS2_FLASH_INTERLEAVE 1 /* ... made of 1 chip */
141#define MX1FS2_FLASH_BANK_SIZE 0x01000000 /* size of one flash bank*/
142#define MX1FS2_FLASH_SECT_SIZE 0x00010000 /* size of erase sector */
143#endif
144#define MX1FS2_FLASH_BASE 0x10000000 /* location of flash memory */
145#define MX1FS2_FLASH_UNLOCK 1 /* perform hw unlock first */
146
147/* This should be defined if CFI FLASH device is present. Actually benefit
148 is not so clear to me. In other words we can provide more informations
149 to user, but this expects more complex flash handling we do not provide
150 now.*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#undef CONFIG_SYS_FLASH_CFI
wdenk281e00a2004-08-01 22:48:16 +0000152
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* timeout for Erase operation */
154#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* timeout for Write operation */
wdenk281e00a2004-08-01 22:48:16 +0000155
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_FLASH_BASE MX1FS2_FLASH_BASE
wdenk281e00a2004-08-01 22:48:16 +0000157
158/*
159 * This is setting for JFFS2 support in u-boot.
160 * Right now there is no gain for user, but later on booting kernel might be
161 * possible. Consider using XIP kernel running from flash to save RAM
162 * footprint.
Jon Loeliger7f5c0152007-07-10 09:38:02 -0500163 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
wdenk281e00a2004-08-01 22:48:16 +0000164 */
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200165
166/*
167 * JFFS2 partitions
168 */
169/* No command line, one static partition, whole device */
170/*
Stefan Roese68d7d652009-03-19 13:30:36 +0100171#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200172#define CONFIG_JFFS2_DEV "nor0"
173#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
174#define CONFIG_JFFS2_PART_OFFSET 0x00050000
175*/
176
177/* mtdparts command line support */
178/* Note: fake mtd_id used, no linux mtd map file */
Stefan Roese68d7d652009-03-19 13:30:36 +0100179#define CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200180#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
181#define CONFIG_FLASH_CFI_MTD
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200182#define MTDIDS_DEFAULT "nor0=mx1fs2-0"
183
184#ifdef BUS32BIT_VERSION
185#define MTDPARTS_DEFAULT "mtdparts=mx1fs2-0:2m@5m(part0),5m@9m(part1)"
186#else
187#define MTDPARTS_DEFAULT "mtdparts=mx1fs2-0:-@320k(jffs2)"
188#endif
wdenk281e00a2004-08-01 22:48:16 +0000189
190/*
191 * Environment setup. Definitions of monitor location and size with
192 * definition of environment setup ends up in 2 possibilities.
193 * 1. Embeded environment - in u-boot code is space for environment
194 * 2. Environment is read from predefined sector of flash
195 * Right now we support 2. possiblity, but expecting no env placed
196 * on mentioned address right now. This also needs to provide whole
197 * sector for it - for us 256Kb is really waste of memory. U-boot uses
198 * default env. and until kernel parameters could be sent to kernel
199 * env. has no sense to us.
200 */
201
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_MONITOR_BASE 0x10000000
203#define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128b ( 1 flash sector ) */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200204#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200205#define CONFIG_ENV_ADDR 0x10020000 /* absolute address for now */
206#define CONFIG_ENV_SIZE 0x20000
wdenk281e00a2004-08-01 22:48:16 +0000207
208#define CONFIG_ENV_OVERWRITE 1 /* env is not writable now */
209
210/* Setup CS4 and CS5 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_GIUS_A_VAL 0x0003fffe
wdenk281e00a2004-08-01 22:48:16 +0000212
213/*
214 * CSxU_VAL:
215 * 63| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x|32
216 * |DTACK_SEL|0|BCD | BCS | PSZ|PME|SYNC| DOL | CNC| WSC | 0| WWS | EDC |
217 *
218 * CSxL_VAL:
219 * 31| x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x | x x x x| 0
220 * | OEA | OEN | WEA | WEN | CSA |EBC| DSZ | 0|SP|0|WP| 0 0|PA|CSEN|
221 */
222
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_CS0U_VAL 0x00008C00
224#define CONFIG_SYS_CS0L_VAL 0x22222601
225#define CONFIG_SYS_CS1U_VAL 0x00008C00
226#define CONFIG_SYS_CS1L_VAL 0x22222301
227#define CONFIG_SYS_CS4U_VAL 0x00008C00
228#define CONFIG_SYS_CS4L_VAL 0x22222301
229#define CONFIG_SYS_CS5U_VAL 0x00008C00
230#define CONFIG_SYS_CS5L_VAL 0x22222301
wdenk281e00a2004-08-01 22:48:16 +0000231
232/* f_{dpll}=2*f{ref}*(MFI+MFN/(MFD+1))/(PD+1)
233 f_ref=16,777MHz
234
235 0x002a141f: 191,9944MHz
236 0x040b2007: 144MHz
237 0x042a141f: 96MHz
238 0x0811140d: 64MHz
239 0x040e200e: 150MHz
240 0x00321431: 200MHz
241
242 0x08001800: 64MHz mit 16er Quarz
243 0x04001800: 96MHz mit 16er Quarz
244 0x04002400: 144MHz mit 16er Quarz
245
246 31 |x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x|x x x x| 0
247 |XXX|--PD---|-------MFD---------|XXX|--MFI--|-----MFN-----------| */
248
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_MPCTL0_VAL 0x07E723AD
250#define CONFIG_SYS_MPCTL1_VAL 0x00000040
251#define CONFIG_SYS_PCDR_VAL 0x00010005
252#define CONFIG_SYS_GPCR_VAL 0x00000FFB
wdenk281e00a2004-08-01 22:48:16 +0000253
254#define USE_16M_OSZI /* If you have one, you want to use it
255 The internal 32kHz oszillator jitters */
256#ifdef USE_16M_OSZI
257
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_SPCTL0_VAL 0x04001401
259#define CONFIG_SYS_SPCTL1_VAL 0x0C000040
260#define CONFIG_SYS_CSCR_VAL 0x07030003
wdenk281e00a2004-08-01 22:48:16 +0000261#define CONFIG_SYS_CLK_FREQ 16780000
262#define CONFIG_SYSPLL_CLK_FREQ 16000000
263
264#else
265
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_SPCTL0_VAL 0x07E716D1
267#define CONFIG_SYS_CSCR_VAL 0x06000003
wdenk281e00a2004-08-01 22:48:16 +0000268#define CONFIG_SYS_CLK_FREQ 16780000
269#define CONFIG_SYSPLL_CLK_FREQ 16780000
270
271#endif
272
273/*
274 * Well this has to be defined, but on the other hand it is used differently
275 * one may expect. For instance loadb command do not cares :-)
276 * So advice is - do not relay on this...
277 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_LOAD_ADDR 0x08400000
wdenk281e00a2004-08-01 22:48:16 +0000279
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_FMCR_VAL 0x00000003 /* Reset Default */
wdenk281e00a2004-08-01 22:48:16 +0000281
282/* Bit[0:3] contain PERCLK1DIV for UART 1
283 0x000b00b ->b<- -> 192MHz/12=16MHz
284 0x000b00b ->8<- -> 144MHz/09=16MHz
285 0x000b00b ->3<- -> 64MHz/4=16MHz */
286
287#ifdef _CONFIG_UART1
Jean-Christophe PLAGNIOL-VILLARDd3e55d02009-03-30 18:58:38 +0200288#define CONFIG_IMX_SERIAL
wdenk281e00a2004-08-01 22:48:16 +0000289#define CONFIG_IMX_SERIAL1
290#elif defined _CONFIG_UART2
Jean-Christophe PLAGNIOL-VILLARDd3e55d02009-03-30 18:58:38 +0200291#define CONFIG_IMX_SERIAL
wdenk281e00a2004-08-01 22:48:16 +0000292#define CONFIG_IMX_SERIAL2
293#elif defined _CONFIG_UART3 | defined _CONFIG_UART4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_NS16550
295#define CONFIG_SYS_NS16550_SERIAL
296#define CONFIG_SYS_NS16550_CLK 3686400
297#define CONFIG_SYS_NS16550_REG_SIZE 1
wdenk281e00a2004-08-01 22:48:16 +0000298#define CONFIG_CONS_INDEX 1
299#ifdef _CONFIG_UART3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_NS16550_COM1 0x15000000
wdenk281e00a2004-08-01 22:48:16 +0000301#elif defined _CONFIG_UART4
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_NS16550_COM1 0x16000000
wdenk281e00a2004-08-01 22:48:16 +0000303#endif
304#endif
305
306#endif /* __CONFIG_H */