Patrick Delaunay | 22929e1 | 2018-10-26 09:02:52 +0200 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 2 | # |
Stephen Warren | 89c1e2d | 2016-06-17 09:43:58 -0600 | [diff] [blame] | 3 | # Copyright (c) 2016, NVIDIA CORPORATION. |
| 4 | # |
Stephen Warren | 89c1e2d | 2016-06-17 09:43:58 -0600 | [diff] [blame] | 5 | |
| 6 | obj-$(CONFIG_DM_RESET) += reset-uclass.o |
Stephen Warren | 4581b71 | 2016-06-17 09:43:59 -0600 | [diff] [blame] | 7 | obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset.o |
| 8 | obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o |
Patrice Chotard | 584861f | 2017-03-22 10:54:03 +0100 | [diff] [blame] | 9 | obj-$(CONFIG_STI_RESET) += sti-reset.o |
Patrice Chotard | 23a0641 | 2017-09-13 18:00:07 +0200 | [diff] [blame] | 10 | obj-$(CONFIG_STM32_RESET) += stm32-reset.o |
Stephen Warren | fe60f06 | 2016-09-13 10:45:58 -0600 | [diff] [blame] | 11 | obj-$(CONFIG_TEGRA_CAR_RESET) += tegra-car-reset.o |
Stephen Warren | 4dd99d1 | 2016-08-08 11:28:25 -0600 | [diff] [blame] | 12 | obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o |
Andreas Dannenberg | 65c8a79 | 2018-08-27 15:57:41 +0530 | [diff] [blame] | 13 | obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o |
Álvaro Fernández Rojas | 18393f7 | 2017-05-03 15:10:21 +0200 | [diff] [blame] | 14 | obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o |
Masahiro Yamada | 4fb96c4 | 2016-10-08 13:25:31 +0900 | [diff] [blame] | 15 | obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o |
maxims@google.com | 858d497 | 2017-04-17 12:00:24 -0700 | [diff] [blame] | 16 | obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o |
Elaine Zhang | 760188c | 2017-12-19 18:22:37 +0800 | [diff] [blame] | 17 | obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o |
Neil Armstrong | 20367bb | 2018-03-29 14:55:25 +0200 | [diff] [blame] | 18 | obj-$(CONFIG_RESET_MESON) += reset-meson.o |
Dinh Nguyen | 2ac7188 | 2018-04-04 17:18:20 -0500 | [diff] [blame] | 19 | obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o |
Weijie Gao | 3e066bc | 2018-12-20 16:12:51 +0800 | [diff] [blame^] | 20 | obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o |