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Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +01001/*
2 * [origin: Linux kernel drivers/watchdog/at91sam9_wdt.c]
3 *
4 * Watchdog driver for Atmel AT91SAM9x processors.
5 *
6 * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
7 * Copyright (C) 2008 Renaud CERRATO r.cerrato@til-technologies.fr
8 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02009 * SPDX-License-Identifier: GPL-2.0+
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +010010 */
11
12/*
13 * The Watchdog Timer Mode Register can be only written to once. If the
14 * timeout need to be set from U-Boot, be sure that the bootstrap doesn't
15 * write to this register. Inform Linux to it too
16 */
17
18#include <common.h>
19#include <watchdog.h>
20#include <asm/arch/hardware.h>
Reinhard Meyer7f6ed7f2011-02-04 20:17:33 +010021#include <asm/io.h>
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +010022#include <asm/arch/at91_wdt.h>
23
24/*
25 * AT91SAM9 watchdog runs a 12bit counter @ 256Hz,
26 * use this to convert a watchdog
27 * value from/to milliseconds.
28 */
29#define ms_to_ticks(t) (((t << 8) / 1000) - 1)
30#define ticks_to_ms(t) (((t + 1) * 1000) >> 8)
31
32/* Hardware timeout in seconds */
Heiko Schocher7bae0d62015-01-21 08:38:22 +010033#if !defined(CONFIG_AT91_HW_WDT_TIMEOUT)
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +010034#define WDT_HW_TIMEOUT 2
Heiko Schocher7bae0d62015-01-21 08:38:22 +010035#else
36#define WDT_HW_TIMEOUT CONFIG_AT91_HW_WDT_TIMEOUT
37#endif
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +010038
39/*
40 * Set the watchdog time interval in 1/256Hz (write-once)
41 * Counter is 12 bit.
42 */
43static int at91_wdt_settimeout(unsigned int timeout)
44{
45 unsigned int reg;
Reinhard Meyer372f2782010-11-03 15:47:20 +010046 at91_wdt_t *wd = (at91_wdt_t *) ATMEL_BASE_WDT;
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +010047
48 /* Check if disabled */
Achim Ehrlichf936aa02010-03-17 14:50:29 +010049 if (readl(&wd->mr) & AT91_WDT_MR_WDDIS) {
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +010050 printf("sorry, watchdog is disabled\n");
51 return -1;
52 }
53
54 /*
55 * All counting occurs at SLOW_CLOCK / 128 = 256 Hz
56 *
57 * Since WDV is a 12-bit counter, the maximum period is
58 * 4096 / 256 = 16 seconds.
59 */
Achim Ehrlichf936aa02010-03-17 14:50:29 +010060
61 reg = AT91_WDT_MR_WDRSTEN /* causes watchdog reset */
62 | AT91_WDT_MR_WDDBGHLT /* disabled in debug mode */
63 | AT91_WDT_MR_WDD(0xfff) /* restart at any time */
64 | AT91_WDT_MR_WDV(timeout); /* timer value */
65
66 writel(reg, &wd->mr);
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +010067
68 return 0;
69}
70
71void hw_watchdog_reset(void)
72{
Reinhard Meyer372f2782010-11-03 15:47:20 +010073 at91_wdt_t *wd = (at91_wdt_t *) ATMEL_BASE_WDT;
Achim Ehrlichf936aa02010-03-17 14:50:29 +010074 writel(AT91_WDT_CR_WDRSTT | AT91_WDT_CR_KEY, &wd->cr);
Jean-Christophe PLAGNIOL-VILLARD843a2652009-03-27 23:26:42 +010075}
76
77void hw_watchdog_init(void)
78{
79 /* 16 seconds timer, resets enabled */
80 at91_wdt_settimeout(ms_to_ticks(WDT_HW_TIMEOUT * 1000));
81}