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TsiChung Liew8e585f02007-06-18 13:50:13 -05001/*
TsiChungLiew2bd806f2007-07-05 23:17:36 -05002 * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
TsiChung Liew8e585f02007-06-18 13:50:13 -05003 * TsiChung Liew, Tsi-Chung.Liew@freescale.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 */
24
25/*
26 * Minimal serial functions needed to use one of the uart ports
27 * as serial console interface.
28 */
29
30#include <common.h>
Wolfgang Denk3e66c072007-08-19 10:27:34 +020031
TsiChungLiew2bd806f2007-07-05 23:17:36 -050032#include <asm/immap.h>
33#include <asm/uart.h>
TsiChung Liew8e585f02007-06-18 13:50:13 -050034
35DECLARE_GLOBAL_DATA_PTR;
36
TsiChungLiew8d1d66a2007-08-05 03:55:21 -050037extern void uart_port_conf(void);
38
TsiChung Liew8e585f02007-06-18 13:50:13 -050039int serial_init(void)
40{
41 volatile uart_t *uart;
42 u32 counter;
43
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044 uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
TsiChung Liew8e585f02007-06-18 13:50:13 -050045
TsiChungLiew8d1d66a2007-08-05 03:55:21 -050046 uart_port_conf();
47
TsiChung Liew8e585f02007-06-18 13:50:13 -050048 /* write to SICR: SIM2 = uart mode,dcd does not affect rx */
49 uart->ucr = UART_UCR_RESET_RX;
50 uart->ucr = UART_UCR_RESET_TX;
51 uart->ucr = UART_UCR_RESET_ERROR;
52 uart->ucr = UART_UCR_RESET_MR;
53 __asm__("nop");
54
55 uart->uimr = 0;
56
57 /* write to CSR: RX/TX baud rate from timers */
58 uart->ucsr = (UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK);
59
60 uart->umr = (UART_UMR_BC_8 | UART_UMR_PM_NONE);
61 uart->umr = UART_UMR_SB_STOP_BITS_1;
62
63 /* Setting up BaudRate */
TsiChung Liew81cc3232008-05-29 12:21:54 -050064 counter = (u32) ((gd->bus_clk / 32) + (gd->baudrate / 2));
65 counter = counter / gd->baudrate;
TsiChung Liew8e585f02007-06-18 13:50:13 -050066
67 /* write to CTUR: divide counter upper byte */
68 uart->ubg1 = (u8) ((counter & 0xff00) >> 8);
69 /* write to CTLR: divide counter lower byte */
70 uart->ubg2 = (u8) (counter & 0x00ff);
71
72 uart->ucr = (UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED);
73
74 return (0);
75}
76
77void serial_putc(const char c)
78{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079 volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
TsiChung Liew8e585f02007-06-18 13:50:13 -050080
81 if (c == '\n')
82 serial_putc('\r');
83
84 /* Wait for last character to go. */
85 while (!(uart->usr & UART_USR_TXRDY)) ;
86
87 uart->utb = c;
88}
89
90void serial_puts(const char *s)
91{
92 while (*s) {
93 serial_putc(*s++);
94 }
95}
96
97int serial_getc(void)
98{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099 volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
TsiChung Liew8e585f02007-06-18 13:50:13 -0500100
101 /* Wait for a character to arrive. */
102 while (!(uart->usr & UART_USR_RXRDY)) ;
103 return uart->urb;
104}
105
106int serial_tstc(void)
107{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108 volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
TsiChung Liew8e585f02007-06-18 13:50:13 -0500109
110 return (uart->usr & UART_USR_RXRDY);
111}
112
113void serial_setbrg(void)
114{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115 volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
TsiChung Liew8e585f02007-06-18 13:50:13 -0500116 u32 counter;
117
Richard Retanubun92d3e6e2009-01-23 11:44:30 -0500118 /* Setting up BaudRate */
119 counter = (u32) ((gd->bus_clk / 32) + (gd->baudrate / 2));
120 counter = counter / gd->baudrate;
TsiChung Liew8e585f02007-06-18 13:50:13 -0500121
122 /* write to CTUR: divide counter upper byte */
123 uart->ubg1 = ((counter & 0xff00) >> 8);
124 /* write to CTLR: divide counter lower byte */
125 uart->ubg2 = (counter & 0x00ff);
126
127 uart->ucr = UART_UCR_RESET_RX;
128 uart->ucr = UART_UCR_RESET_TX;
129
130 uart->ucr = UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED;
131}