goda.yusuke | 6a8a5dc | 2008-03-05 17:08:33 +0900 | [diff] [blame] | 1 | /* |
| 2 | * AX88796L(NE2000) support |
| 3 | * |
| 4 | * (c) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; either version 2 of |
| 9 | * the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 19 | * MA 02111-1307 USA |
| 20 | * |
| 21 | */ |
| 22 | |
| 23 | #ifndef __DRIVERS_AX88796L_H__ |
| 24 | #define __DRIVERS_AX88796L_H__ |
| 25 | |
Jean-Christophe PLAGNIOL-VILLARD | 4acbc6c | 2008-04-24 07:57:16 +0200 | [diff] [blame] | 26 | #define DP_DATA (0x10 << 1) |
| 27 | #define START_PG 0x40 /* First page of TX buffer */ |
| 28 | #define START_PG2 0x48 |
| 29 | #define STOP_PG 0x80 /* Last page +1 of RX ring */ |
| 30 | #define TX_PAGES 12 |
| 31 | #define RX_START (START_PG+TX_PAGES) |
| 32 | #define RX_END STOP_PG |
goda.yusuke | 6a8a5dc | 2008-03-05 17:08:33 +0900 | [diff] [blame] | 33 | |
| 34 | #define AX88796L_BASE_ADDRESS CONFIG_DRIVER_NE2000_BASE |
Jean-Christophe PLAGNIOL-VILLARD | 4acbc6c | 2008-04-24 07:57:16 +0200 | [diff] [blame] | 35 | #define AX88796L_BYTE_ACCESS 0x00001000 |
| 36 | #define AX88796L_OFFSET 0x00000400 |
| 37 | #define AX88796L_ADDRESS_BYTE AX88796L_BASE_ADDRESS + \ |
goda.yusuke | 6a8a5dc | 2008-03-05 17:08:33 +0900 | [diff] [blame] | 38 | AX88796L_BYTE_ACCESS + AX88796L_OFFSET |
Jean-Christophe PLAGNIOL-VILLARD | 4acbc6c | 2008-04-24 07:57:16 +0200 | [diff] [blame] | 39 | #define AX88796L_REG_MEMR AX88796L_ADDRESS_BYTE + (0x14<<1) |
| 40 | #define AX88796L_REG_CR AX88796L_ADDRESS_BYTE + (0x00<<1) |
goda.yusuke | 6a8a5dc | 2008-03-05 17:08:33 +0900 | [diff] [blame] | 41 | |
| 42 | #define AX88796L_CR (*(vu_short *)(AX88796L_REG_CR)) |
Jean-Christophe PLAGNIOL-VILLARD | 4acbc6c | 2008-04-24 07:57:16 +0200 | [diff] [blame] | 43 | #define AX88796L_MEMR (*(vu_short *)(AX88796L_REG_MEMR)) |
goda.yusuke | 6a8a5dc | 2008-03-05 17:08:33 +0900 | [diff] [blame] | 44 | |
| 45 | #define EECS_HIGH (AX88796L_MEMR |= 0x10) |
| 46 | #define EECS_LOW (AX88796L_MEMR &= 0xef) |
| 47 | #define EECLK_HIGH (AX88796L_MEMR |= 0x80) |
| 48 | #define EECLK_LOW (AX88796L_MEMR &= 0x7f) |
| 49 | #define EEDI_HIGH (AX88796L_MEMR |= 0x20) |
| 50 | #define EEDI_LOW (AX88796L_MEMR &= 0xdf) |
| 51 | #define EEDO ((AX88796L_MEMR & 0x40)>>6) |
| 52 | |
| 53 | #define PAGE0_SET (AX88796L_CR &= 0x3f) |
| 54 | #define PAGE1_SET (AX88796L_CR = (AX88796L_CR & 0x3f) | 0x40) |
| 55 | |
Jean-Christophe PLAGNIOL-VILLARD | 4acbc6c | 2008-04-24 07:57:16 +0200 | [diff] [blame] | 56 | #define BIT_DUMMY 0 |
goda.yusuke | 6a8a5dc | 2008-03-05 17:08:33 +0900 | [diff] [blame] | 57 | #define MAC_EEP_READ 1 |
| 58 | #define MAC_EEP_WRITE 2 |
| 59 | #define MAC_EEP_ERACE 3 |
| 60 | #define MAC_EEP_EWEN 4 |
| 61 | #define MAC_EEP_EWDS 5 |
| 62 | |
| 63 | /* R7780MP Specific code */ |
| 64 | #if defined(CONFIG_R7780MP) |
Jean-Christophe PLAGNIOL-VILLARD | 4acbc6c | 2008-04-24 07:57:16 +0200 | [diff] [blame] | 65 | #define ISA_OFFSET 0x1400 |
| 66 | #define DP_IN(_b_, _o_, _d_) (_d_) = \ |
goda.yusuke | 6a8a5dc | 2008-03-05 17:08:33 +0900 | [diff] [blame] | 67 | *( (vu_short *) ((_b_) + ((_o_) * 2) + ISA_OFFSET)) |
| 68 | #define DP_OUT(_b_, _o_, _d_) \ |
| 69 | *((vu_short *)((_b_) + ((_o_) * 2) + ISA_OFFSET)) = (_d_) |
Jean-Christophe PLAGNIOL-VILLARD | 4acbc6c | 2008-04-24 07:57:16 +0200 | [diff] [blame] | 70 | #define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_short *) ((_b_) + ISA_OFFSET)) |
| 71 | #define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_) |
goda.yusuke | 6a8a5dc | 2008-03-05 17:08:33 +0900 | [diff] [blame] | 72 | #else |
| 73 | /* Please change for your target boards */ |
Jean-Christophe PLAGNIOL-VILLARD | 4acbc6c | 2008-04-24 07:57:16 +0200 | [diff] [blame] | 74 | #define ISA_OFFSET 0x0000 |
| 75 | #define DP_IN(_b_, _o_, _d_) (_d_) = *( (vu_short *)((_b_)+(_o_ )+ISA_OFFSET)) |
| 76 | #define DP_OUT(_b_, _o_, _d_) *((vu_short *)((_b_)+(_o_)+ISA_OFFSET)) = (_d_) |
| 77 | #define DP_IN_DATA(_b_, _d_) (_d_) = *( (vu_short *) ((_b_)+ISA_OFFSET)) |
| 78 | #define DP_OUT_DATA(_b_, _d_) *( (vu_short *) ((_b_)+ISA_OFFSET)) = (_d_) |
goda.yusuke | 6a8a5dc | 2008-03-05 17:08:33 +0900 | [diff] [blame] | 79 | #endif |
| 80 | |
| 81 | |
| 82 | /* |
| 83 | * Set 1 bit data |
| 84 | */ |
| 85 | static void ax88796_bitset(u32 bit) |
| 86 | { |
| 87 | /* DATA1 */ |
| 88 | if( bit ) |
| 89 | EEDI_HIGH; |
| 90 | else |
| 91 | EEDI_LOW; |
| 92 | |
| 93 | EECLK_LOW; |
| 94 | udelay(1000); |
| 95 | EECLK_HIGH; |
| 96 | udelay(1000); |
| 97 | EEDI_LOW; |
| 98 | } |
| 99 | |
| 100 | /* |
| 101 | * Get 1 bit data |
| 102 | */ |
| 103 | static u8 ax88796_bitget(void) |
| 104 | { |
| 105 | u8 bit; |
| 106 | |
| 107 | EECLK_LOW; |
| 108 | udelay(1000); |
| 109 | /* DATA */ |
| 110 | bit = EEDO; |
| 111 | EECLK_HIGH; |
| 112 | udelay(1000); |
| 113 | |
| 114 | return bit; |
| 115 | } |
| 116 | |
| 117 | /* |
| 118 | * Send COMMAND to EEPROM |
| 119 | */ |
| 120 | static void ax88796_eep_cmd(u8 cmd) |
| 121 | { |
| 122 | ax88796_bitset(BIT_DUMMY); |
| 123 | switch(cmd){ |
| 124 | case MAC_EEP_READ: |
| 125 | ax88796_bitset(1); |
| 126 | ax88796_bitset(1); |
| 127 | ax88796_bitset(0); |
| 128 | break; |
| 129 | |
| 130 | case MAC_EEP_WRITE: |
| 131 | ax88796_bitset(1); |
| 132 | ax88796_bitset(0); |
| 133 | ax88796_bitset(1); |
| 134 | break; |
| 135 | |
| 136 | case MAC_EEP_ERACE: |
| 137 | ax88796_bitset(1); |
| 138 | ax88796_bitset(1); |
| 139 | ax88796_bitset(1); |
| 140 | break; |
| 141 | |
| 142 | case MAC_EEP_EWEN: |
| 143 | ax88796_bitset(1); |
| 144 | ax88796_bitset(0); |
| 145 | ax88796_bitset(0); |
| 146 | break; |
| 147 | |
| 148 | case MAC_EEP_EWDS: |
| 149 | ax88796_bitset(1); |
| 150 | ax88796_bitset(0); |
| 151 | ax88796_bitset(0); |
| 152 | break; |
| 153 | default: |
| 154 | break; |
| 155 | } |
| 156 | } |
| 157 | |
| 158 | static void ax88796_eep_setaddr(u16 addr) |
| 159 | { |
| 160 | int i ; |
| 161 | for( i = 7 ; i >= 0 ; i-- ) |
| 162 | ax88796_bitset(addr & (1 << i)); |
| 163 | } |
| 164 | |
| 165 | /* |
| 166 | * Get data from EEPROM |
| 167 | */ |
| 168 | static u16 ax88796_eep_getdata(void) |
| 169 | { |
| 170 | ushort data = 0; |
| 171 | int i; |
| 172 | |
| 173 | ax88796_bitget(); /* DUMMY */ |
| 174 | for( i = 0 ; i < 16 ; i++ ){ |
| 175 | data <<= 1; |
| 176 | data |= ax88796_bitget(); |
| 177 | } |
| 178 | return data; |
| 179 | } |
| 180 | |
| 181 | static void ax88796_mac_read(u8 *buff) |
| 182 | { |
| 183 | int i ; |
| 184 | u16 data, addr = 0; |
| 185 | |
| 186 | for( i = 0 ; i < 3; i++ ) |
| 187 | { |
| 188 | EECS_HIGH; |
| 189 | EEDI_LOW; |
| 190 | udelay(1000); |
| 191 | /* READ COMMAND */ |
| 192 | ax88796_eep_cmd(MAC_EEP_READ); |
| 193 | /* ADDRESS */ |
| 194 | ax88796_eep_setaddr(addr++); |
| 195 | /* GET DATA */ |
| 196 | data = ax88796_eep_getdata(); |
| 197 | *buff++ = (uchar)(data & 0xff); |
| 198 | *buff++ = (uchar)((data >> 8) & 0xff); |
| 199 | EECLK_LOW; |
| 200 | EEDI_LOW; |
| 201 | EECS_LOW; |
| 202 | } |
| 203 | } |
| 204 | |
| 205 | int get_prom(u8* mac_addr) |
| 206 | { |
| 207 | u8 prom[32]; |
| 208 | int i; |
| 209 | |
| 210 | ax88796_mac_read(prom); |
| 211 | for (i = 0; i < 6; i++){ |
| 212 | mac_addr[i] = prom[i]; |
| 213 | } |
| 214 | return 1; |
| 215 | } |
| 216 | |
| 217 | #endif /* __DRIVERS_AX88796L_H__ */ |