| Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Rick Chen | 6020faf | 2017-12-26 13:55:51 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2017 Andes Technology Corporation |
| 4 | * Rick Chen, Andes Technology Corporation <rick@andestech.com> |
| Rick Chen | 6020faf | 2017-12-26 13:55:51 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __ASM_RISCV_SYSTEM_H |
| 8 | #define __ASM_RISCV_SYSTEM_H |
| 9 | |
| Simon Glass | 7fe32b3 | 2022-03-04 08:43:05 -0700 | [diff] [blame] | 10 | struct event; |
| 11 | |
| Rick Chen | 6020faf | 2017-12-26 13:55:51 +0800 | [diff] [blame] | 12 | /* |
| 13 | * Interrupt configuring macros. |
| 14 | * |
| 15 | * TODO |
| 16 | * |
| 17 | */ |
| 18 | |
| Simon Glass | 7fe32b3 | 2022-03-04 08:43:05 -0700 | [diff] [blame] | 19 | /* Hook to set up the CPU (called from SPL too) */ |
| 20 | int riscv_cpu_setup(void *ctx, struct event *event); |
| 21 | |
| Rick Chen | 6020faf | 2017-12-26 13:55:51 +0800 | [diff] [blame] | 22 | #endif /* __ASM_RISCV_SYSTEM_H */ |