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Stefan Roese34167a32007-01-18 11:48:10 +01001/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21/************************************************************************
22 * TAISHAN.h - configuration for AMCC 440GX Ref
23 ***********************************************************************/
24
25#ifndef __CONFIG_H
26#define __CONFIG_H
27
28/*-----------------------------------------------------------------------
29 * High Level Configuration Options
30 *----------------------------------------------------------------------*/
31#define CONFIG_TAISHAN 1 /* Board is taishan */
32#define CONFIG_440GX 1 /* Specifc GX support */
33#define CONFIG_4xx 1 /* ... PPC4xx family */
34#undef CFG_DRAM_TEST /* Disable-takes long time! */
35#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
36
37#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
38#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
39
40/*-----------------------------------------------------------------------
41 * Base addresses -- Note these are effective addresses where the
42 * actual resources get mapped (not physical addresses)
43 *----------------------------------------------------------------------*/
44#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
45#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */
46#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */
47#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
48#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
49#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
50#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
51
52#define CFG_EBC0_FLASH_BASE CFG_FLASH_BASE
53#define CFG_EBC1_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x01000000)
54#define CFG_EBC2_LCM_BASE (CFG_PERIPHERAL_BASE + 0x02000000)
55#define CFG_EBC3_CONN_BASE (CFG_PERIPHERAL_BASE + 0x08000000)
56
57#define CFG_GPIO_BASE (CFG_PERIPHERAL_BASE + 0x00000700)
58
59/*-----------------------------------------------------------------------
60 * Initial RAM & stack pointer (placed in internal SRAM)
61 *----------------------------------------------------------------------*/
62#define CFG_TEMP_STACK_OCM 1
63#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
64#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
65#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM*/
66#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data*/
67
68#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
69#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
70#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
71
72#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/
73#define CFG_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc*/
74
75/*-----------------------------------------------------------------------
76 * Serial Port
77 *----------------------------------------------------------------------*/
78#define CONFIG_UART1_CONSOLE 1 /* use of UART1 as console */
79#define CONFIG_SERIAL_MULTI 1 /* enable serial multi support */
80#define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */
81#define CONFIG_BAUDRATE 115200
82
83#define CFG_BAUDRATE_TABLE \
84 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
85
86/*-----------------------------------------------------------------------
87 * Environment
88 *----------------------------------------------------------------------*/
89#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
90
91/*-----------------------------------------------------------------------
92 * FLASH related
93 *----------------------------------------------------------------------*/
94#define CFG_FLASH_CFI
95#define CFG_FLASH_CFI_DRIVER
96#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
97#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
98
99#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
100#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
101#define CFG_MAX_FLASH_SECT 1024 /* sectors per device */
102
103#undef CFG_FLASH_CHECKSUM
104#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
105#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
106
107#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
108#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
109#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
110
111/* Address and size of Redundant Environment Sector */
112#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
113#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
114
115/*-----------------------------------------------------------------------
116 * E2PROM bootstrap configure value
117 *----------------------------------------------------------------------*/
118
119/*
120 * 800/133/66
121 * IIC 0~15: 86 78 11 6a 61 A7 04 62 00 00 00 00 00 00 00 00
122 */
123
124/*
125 * 800/160/80
126 * IIC 0~15: 86 78 c1 a6 09 67 04 63 00 00 00 00 00 00 00 00
127 */
128
129/*-----------------------------------------------------------------------
130 * DDR SDRAM
131 *----------------------------------------------------------------------*/
132#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
133#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0 */
134#define CFG_SDRAM0_TR0 0xC10A401A
135#undef CONFIG_SDRAM_ECC /* enable ECC support */
136
137/*-----------------------------------------------------------------------
138 * I2C
139 *----------------------------------------------------------------------*/
140#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
141#undef CONFIG_SOFT_I2C /* I2C bit-banged */
142#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
143#define CFG_I2C_SLAVE 0x7F
144
145#undef CFG_I2C_MULTI_EEPROMS
146#define CFG_I2C_EEPROM_ADDR 0x50
147#define CFG_I2C_EEPROM_ADDR_LEN 1
148#define CFG_EEPROM_PAGE_WRITE_ENABLE
149#define CFG_EEPROM_PAGE_WRITE_BITS 3
150#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
151
152#define CFG_BOOTSTRAP_IIC_ADDR 0x50
153
154/* I2C SYSMON (LM75, AD7414 is almost compatible) */
155#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
156#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
157#define CFG_DTT_MAX_TEMP 70
158#define CFG_DTT_LOW_TEMP -30
159#define CFG_DTT_HYSTERESIS 3
160
161/*-----------------------------------------------------------------------
162 * Environment
163 *----------------------------------------------------------------------*/
164
165#define CONFIG_PREBOOT "echo;" \
166 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
167 "echo"
168
169#undef CONFIG_BOOTARGS
170
171#define CONFIG_EXTRA_ENV_SETTINGS \
172 "netdev=eth0\0" \
173 "hostname=taishan\0" \
174 "nfsargs=setenv bootargs root=/dev/nfs rw " \
175 "nfsroot=${serverip}:${rootpath}\0" \
176 "ramargs=setenv bootargs root=/dev/ram rw\0" \
177 "addip=setenv bootargs ${bootargs} " \
178 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
179 ":${hostname}:${netdev}:off panic=1\0" \
180 "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
181 "flash_nfs=run nfsargs addip addtty;" \
182 "bootm ${kernel_addr}\0" \
183 "flash_self=run ramargs addip addtty;" \
184 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
185 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
186 "bootm\0" \
187 "rootpath=/opt/eldk/ppc_4xx\0" \
188 "bootfile=/tftpboot/taishan/uImage\0" \
189 "kernel_addr=fc000000\0" \
190 "ramdisk_addr=fc180000\0" \
Stefan Roese5a753f92007-02-07 16:51:08 +0100191 "initrd_high=30000000\0" \
Stefan Roese34167a32007-01-18 11:48:10 +0100192 "load=tftp 100000 /tftpboot/taishan/u-boot.bin\0" \
193 "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
194 "cp.b 100000 fffc0000 40000;" \
195 "setenv filesize;saveenv\0" \
196 "upd=run load;run update\0" \
197 "fixedip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
198 "$(gatewayip):$(netmask):$(hostname):$(netdev):off panic=1\0" \
199 "dhcp=setenv bootargs $(bootargs) ip=dhcp\0" \
200 "kozio=bootm 0xffe00000\0" \
201 ""
202#define CONFIG_BOOTCOMMAND "run flash_self"
203
204#if 0
205#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
206#else
207#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
208#endif
209
210#define CONFIG_BAUDRATE 115200
211#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
212#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
213
214/*-----------------------------------------------------------------------
215 * Networking
216 *----------------------------------------------------------------------*/
217#define CONFIG_EMAC_NR_START 2 /* start with EMAC 2 (skip 0&1) */
218#define CONFIG_MII 1 /* MII PHY management */
219#define CONFIG_NET_MULTI 1
220#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
221#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
222#define CONFIG_PHY2_ADDR 0x1
223#define CONFIG_PHY3_ADDR 0x3
224#define CONFIG_ET1011C_PHY 1
225#define CONFIG_HAS_ETH0
226#define CONFIG_HAS_ETH1
227#define CONFIG_HAS_ETH2
228#define CONFIG_HAS_ETH3
229#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
230#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
231#define CONFIG_PHY_RESET_DELAY 1000
232#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
233
234#define CONFIG_NETCONSOLE /* include NetConsole support */
235
236/*-----------------------------------------------------------------------
237 * Console/Commands/Parser
238 *----------------------------------------------------------------------*/
239#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
240 CFG_CMD_ASKENV | \
241 CFG_CMD_DHCP | \
242 CFG_CMD_DIAG | \
243 CFG_CMD_DTT | \
244 CFG_CMD_ELF | \
245 CFG_CMD_EEPROM | \
246 CFG_CMD_I2C | \
247 CFG_CMD_IRQ | \
248 CFG_CMD_MII | \
249 CFG_CMD_NET | \
250 CFG_CMD_NFS | \
251 CFG_CMD_PCI | \
252 CFG_CMD_PING | \
253 CFG_CMD_REGINFO)
254
255/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
256#include <cmd_confdefs.h>
257
258#undef CONFIG_WATCHDOG /* watchdog disabled */
259
260/*-----------------------------------------------------------------------
261 * Miscellaneous configurable options
262 *----------------------------------------------------------------------*/
263#define CFG_LONGHELP /* undef to save memory */
264#define CFG_PROMPT "=> " /* Monitor Command Prompt */
265#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
266#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
267#else
268#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
269#endif
270#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
271#define CFG_MAXARGS 16 /* max number of command args */
272#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
273
274#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
275#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
276
277#define CFG_LOAD_ADDR 0x100000 /* default load address */
278#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
279
280#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
281
282#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
283#define CONFIG_LOOPW 1 /* enable loopw command */
284#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
285#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
286#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
287
288/*-----------------------------------------------------------------------
289 * PCI stuff
290 *-----------------------------------------------------------------------
291 */
292/* General PCI */
293#define CONFIG_PCI /* include pci support */
294#define CONFIG_PCI_PNP /* do pci plug-and-play */
295#define CONFIG_EEPRO100 1 /* include PCI EEPRO100 */
296#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
297#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
298
299/* Board-specific PCI */
300#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
301#define CFG_PCI_TARGET_INIT /* let board init pci target */
302
303#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
304#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
305
306/*
307 * For booting Linux, the board info and command line data
308 * have to be in the first 8 MB of memory, since this is
309 * the maximum mapped by the Linux kernel during initialization.
310 */
311#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
312
313/*-----------------------------------------------------------------------
314 * Cache Configuration
315 *----------------------------------------------------------------------*/
316#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */
317#define CFG_CACHELINE_SIZE 32 /* ... */
318#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
319#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
320#endif
321
322/*
323 * Internal Definitions
324 *
325 * Boot Flags
326 */
327#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
328#define BOOTFLAG_WARM 0x02 /* Software reboot */
329
330#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
331#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
332#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
333#endif
334#endif /* __CONFIG_H */