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Jon Loeligerdebb7352006-04-26 17:58:56 -05001/*
Jon Loeliger5c9efb32006-04-27 10:15:16 -05002 * Copyright 2006 Freescale Semiconductor.
Jon Loeligerb93775c2006-08-22 18:26:08 -05003 * Jeffrey Brown
Jon Loeligerdebb7352006-04-26 17:58:56 -05004 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
5 */
6
7#ifndef __MPC86xx_H__
8#define __MPC86xx_H__
9
10#define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */
11
Jon Loeliger5c9efb32006-04-27 10:15:16 -050012/*
Jon Loeligerdebb7352006-04-26 17:58:56 -050013 * l2cr values. Look in config_<BOARD>.h for the actual setup
14 */
15#define l2cr 1017
16
17#define L2CR_L2E 0x80000000 /* bit 0 - enable */
18#define L2CR_L2PE 0x40000000 /* bit 1 - data parity */
19#define L2CR_L2I 0x00200000 /* bit 10 - global invalidate bit */
20#define L2CR_L2CTL 0x00100000 /* bit 11 - l2 ram control */
21#define L2CR_L2DO 0x00010000 /* bit 15 - data-only mode */
22#define L2CR_REP 0x00001000 /* bit 19 - l2 replacement alg */
23#define L2CR_HWF 0x00000800 /* bit 20 - hardware flush */
24#define L2CR_L2IP 0x00000001 /* global invalidate in progress */
25
Jon Loeliger5c9efb32006-04-27 10:15:16 -050026/*
Jon Loeligerdebb7352006-04-26 17:58:56 -050027 * BAT settings. Look in config_<BOARD>.h for the actual setup
28 */
29
30#define BATU_BL_128K 0x00000000
31#define BATU_BL_256K 0x00000004
32#define BATU_BL_512K 0x0000000c
33#define BATU_BL_1M 0x0000001c
34#define BATU_BL_2M 0x0000003c
35#define BATU_BL_4M 0x0000007c
36#define BATU_BL_8M 0x000000fc
37#define BATU_BL_16M 0x000001fc
38#define BATU_BL_32M 0x000003fc
39#define BATU_BL_64M 0x000007fc
40#define BATU_BL_128M 0x00000ffc
41#define BATU_BL_256M 0x00001ffc
42#define BATU_BL_512M 0x00003ffc
43#define BATU_BL_1G 0x00007ffc
44#define BATU_BL_2G 0x0000fffc
45#define BATU_BL_4G 0x0001fffc
46
47#define BATU_VS 0x00000002
48#define BATU_VP 0x00000001
49#define BATU_INVALID 0x00000000
50
51#define BATL_WRITETHROUGH 0x00000040
52#define BATL_CACHEINHIBIT 0x00000020
53#define BATL_MEMCOHERENCE 0x00000010
54#define BATL_GUARDEDSTORAGE 0x00000008
55#define BATL_NO_ACCESS 0x00000000
56
57#define BATL_PP_MSK 0x00000003
58#define BATL_PP_00 0x00000000 /* No access */
59#define BATL_PP_01 0x00000001 /* Read-only */
60#define BATL_PP_10 0x00000002 /* Read-write */
61#define BATL_PP_11 0x00000003
62
63#define BATL_PP_NO_ACCESS BATL_PP_00
64#define BATL_PP_RO BATL_PP_01
65#define BATL_PP_RW BATL_PP_10
66
67#define HID0_XBSEN 0x00000100
68#define HID0_HIGH_BAT_EN 0x00800000
69#define HID0_XAEN 0x00020000
70
71#ifndef __ASSEMBLY__
72
Jon Loeligerb93775c2006-08-22 18:26:08 -050073typedef struct {
74 unsigned long freqProcessor;
75 unsigned long freqSystemBus;
Jon Loeligerdebb7352006-04-26 17:58:56 -050076} MPC86xx_SYS_INFO;
77
78#define l1icache_enable icache_enable
79
80void l2cache_enable(void);
81void l1dcache_enable(void);
82
83static __inline__ unsigned long get_hid0 (void)
84{
85 unsigned long hid0;
86 asm volatile("mfspr %0, 1008" : "=r" (hid0) :);
87 return hid0;
88}
89
90static __inline__ unsigned long get_hid1 (void)
91{
92 unsigned long hid1;
93 asm volatile("mfspr %0, 1009" : "=r" (hid1) :);
94 return hid1;
95}
96
97static __inline__ void set_hid0 (unsigned long hid0)
98{
99 asm volatile("mtspr 1008, %0" : : "r" (hid0));
100}
101
102static __inline__ void set_hid1 (unsigned long hid1)
103{
104 asm volatile("mtspr 1009, %0" : : "r" (hid1));
105}
106
107
108static __inline__ unsigned long get_l2cr (void)
109{
110 unsigned long l2cr_val;
111 asm volatile("mfspr %0, 1017" : "=r" (l2cr_val) :);
112 return l2cr_val;
113}
114
115#endif /* _ASMLANGUAGE */
116#endif /* __MPC86xx_H__ */