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stroeseaee2fa22004-12-16 18:17:50 +00001/*
2 * (C) Copyright 2004
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <asm/processor.h>
26#include <command.h>
27
stroeseaee2fa22004-12-16 18:17:50 +000028#define MEM_MCOPT1_INIT_VAL 0x00800000
29#define MEM_RTR_INIT_VAL 0x04070000
30#define MEM_PMIT_INIT_VAL 0x07c00000
31#define MEM_MB0CF_INIT_VAL 0x00082001
32#define MEM_MB1CF_INIT_VAL 0x04082000
33#define MEM_SDTR1_INIT_VAL 0x00854005
34#define SDRAM0_CFG_ENABLE 0x80000000
35
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020036#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 MB */
stroeseaee2fa22004-12-16 18:17:50 +000037
stroeseaee2fa22004-12-16 18:17:50 +000038int board_early_init_f (void)
39{
40#if 0 /* test-only */
Stefan Roese952e7762009-09-24 09:55:50 +020041 mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
42 mtdcr (UIC0ER, 0x00000000); /* disable all ints */
43 mtdcr (UIC0CR, 0x00000010);
44 mtdcr (UIC0PR, 0xFFFF7FF0); /* set int polarities */
45 mtdcr (UIC0TR, 0x00000010); /* set int trigger levels */
46 mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */
stroeseaee2fa22004-12-16 18:17:50 +000047#else
Stefan Roese952e7762009-09-24 09:55:50 +020048 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
49 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
50 mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
51 mtdcr(UIC0PR, 0xFFFFFFF0); /* set int polarities */
52 mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
53 mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
54 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
stroeseaee2fa22004-12-16 18:17:50 +000055#endif
56
57#if 1 /* test-only */
58 /*
59 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
60 */
Stefan Roesed1c3b272009-09-09 16:25:29 +020061 mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
stroeseaee2fa22004-12-16 18:17:50 +000062#endif
63
64 return 0;
65}
66
67
68int misc_init_f (void)
69{
70 return 0; /* dummy implementation */
71}
72
73
74int misc_init_r (void)
75{
Jon Loeligerc508a4c2007-07-09 18:31:28 -050076#if defined(CONFIG_CMD_NAND)
stroeseaee2fa22004-12-16 18:17:50 +000077 /*
78 * Set NAND-FLASH GPIO signals to default
79 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080 out32(GPIO0_OR, in32(GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
81 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND_CE);
stroeseaee2fa22004-12-16 18:17:50 +000082#endif
83
84 return (0);
85}
86
87
88/*
89 * Check Board Identity:
90 */
91int checkboard (void)
92{
Wolfgang Denk77ddac92005-10-13 16:45:02 +020093 char str[64];
stroeseaee2fa22004-12-16 18:17:50 +000094 int i = getenv_r ("serial#", str, sizeof(str));
95
96 puts ("Board: ");
97
98 if (i == -1) {
99 puts ("### No HW ID - assuming G2000");
100 } else {
101 puts(str);
102 }
103
104 putc ('\n');
105
106 return 0;
107}
108
109
110/* -------------------------------------------------------------------------
111 G2000 rev B is an embeded design. we don't read for spd of this version.
112 Doing static SDRAM controller configuration in the following section.
113 ------------------------------------------------------------------------- */
114
115long int init_sdram_static_settings(void)
116{
wdenkefe2a4d2004-12-16 21:44:03 +0000117 /* disable memcontroller so updates work */
Stefan Roeseb306db22009-09-24 14:10:30 +0200118 mtsdram(SDRAM0_CFG, MEM_MCOPT1_INIT_VAL);
119 mtsdram(SDRAM0_RTR, MEM_RTR_INIT_VAL);
120 mtsdram(SDRAM0_PMIT, MEM_PMIT_INIT_VAL);
121 mtsdram(SDRAM0_B0CR, MEM_MB0CF_INIT_VAL);
122 mtsdram(SDRAM0_B1CR, MEM_MB1CF_INIT_VAL);
123 mtsdram(SDRAM0_TR, MEM_SDTR1_INIT_VAL);
stroeseaee2fa22004-12-16 18:17:50 +0000124
wdenkefe2a4d2004-12-16 21:44:03 +0000125 /* SDRAM have a power on delay, 500 micro should do */
126 udelay(500);
Stefan Roeseb306db22009-09-24 14:10:30 +0200127 mtsdram(SDRAM0_CFG, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE);
stroeseaee2fa22004-12-16 18:17:50 +0000128
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129 return (CONFIG_SYS_SDRAM_SIZE); /* CONFIG_SYS_SDRAM_SIZE is in G2000.h */
stroeseaee2fa22004-12-16 18:17:50 +0000130 }
131
132
Becky Bruce9973e3c2008-06-09 16:03:40 -0500133phys_size_t initdram (int board_type)
stroeseaee2fa22004-12-16 18:17:50 +0000134{
135 long int ret;
136
137/* flzt, we can still turn this on in the future */
138/* #ifdef CONFIG_SPD_EEPROM
wdenkefe2a4d2004-12-16 21:44:03 +0000139 ret = spd_sdram ();
stroeseaee2fa22004-12-16 18:17:50 +0000140#else
wdenkefe2a4d2004-12-16 21:44:03 +0000141 ret = init_sdram_static_settings();
stroeseaee2fa22004-12-16 18:17:50 +0000142#endif
143*/
144
145 ret = init_sdram_static_settings();
146
147 return ret;
148}
149
stroeseaee2fa22004-12-16 18:17:50 +0000150#if 0 /* test-only !!! */
151int do_dumpebc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
152{
153 ulong ap, cr;
154
155 printf("\nEBC registers for PPC405GP:\n");
Stefan Roesed1c3b272009-09-09 16:25:29 +0200156 mfebc(PB0AP, ap); mfebc(PB0CR, cr);
stroeseaee2fa22004-12-16 18:17:50 +0000157 printf("0: AP=%08lx CP=%08lx\n", ap, cr);
Stefan Roesed1c3b272009-09-09 16:25:29 +0200158 mfebc(PB1AP, ap); mfebc(PB1CR, cr);
stroeseaee2fa22004-12-16 18:17:50 +0000159 printf("1: AP=%08lx CP=%08lx\n", ap, cr);
Stefan Roesed1c3b272009-09-09 16:25:29 +0200160 mfebc(PB2AP, ap); mfebc(PB2CR, cr);
stroeseaee2fa22004-12-16 18:17:50 +0000161 printf("2: AP=%08lx CP=%08lx\n", ap, cr);
Stefan Roesed1c3b272009-09-09 16:25:29 +0200162 mfebc(PB3AP, ap); mfebc(PB3CR, cr);
stroeseaee2fa22004-12-16 18:17:50 +0000163 printf("3: AP=%08lx CP=%08lx\n", ap, cr);
Stefan Roesed1c3b272009-09-09 16:25:29 +0200164 mfebc(PB4AP, ap); mfebc(PB4CR, cr);
stroeseaee2fa22004-12-16 18:17:50 +0000165 printf("4: AP=%08lx CP=%08lx\n", ap, cr);
166 printf("\n");
167
168 return 0;
169}
170U_BOOT_CMD(
171 dumpebc, 1, 1, do_dumpebc,
Peter Tyser2fb26042009-01-27 18:03:12 -0600172 "Dump all EBC registers",
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200173 ""
stroeseaee2fa22004-12-16 18:17:50 +0000174);
175
176
177int do_dumpdcr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
178{
179 int i;
180
181 printf("\nDevice Configuration Registers (DCR's) for PPC405GP:");
182 for (i=0; i<=0x1e0; i++) {
183 if (!(i % 0x8)) {
184 printf("\n%04x ", i);
185 }
186 printf("%08lx ", get_dcr(i));
187 }
188 printf("\n");
189
190 return 0;
191}
192U_BOOT_CMD(
193 dumpdcr, 1, 1, do_dumpdcr,
Peter Tyser2fb26042009-01-27 18:03:12 -0600194 "Dump all DCR registers",
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200195 ""
stroeseaee2fa22004-12-16 18:17:50 +0000196);
197
198
199int do_dumpspr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
200{
201 printf("\nSpecial Purpose Registers (SPR's) for PPC405GP:");
202 printf("\n%04x %08x ", 947, mfspr(947));
203 printf("\n%04x %08x ", 9, mfspr(9));
204 printf("\n%04x %08x ", 1014, mfspr(1014));
205 printf("\n%04x %08x ", 1015, mfspr(1015));
206 printf("\n%04x %08x ", 1010, mfspr(1010));
207 printf("\n%04x %08x ", 957, mfspr(957));
208 printf("\n%04x %08x ", 1008, mfspr(1008));
209 printf("\n%04x %08x ", 1018, mfspr(1018));
210 printf("\n%04x %08x ", 954, mfspr(954));
211 printf("\n%04x %08x ", 950, mfspr(950));
212 printf("\n%04x %08x ", 951, mfspr(951));
213 printf("\n%04x %08x ", 981, mfspr(981));
214 printf("\n%04x %08x ", 980, mfspr(980));
215 printf("\n%04x %08x ", 982, mfspr(982));
216 printf("\n%04x %08x ", 1012, mfspr(1012));
217 printf("\n%04x %08x ", 1013, mfspr(1013));
218 printf("\n%04x %08x ", 948, mfspr(948));
219 printf("\n%04x %08x ", 949, mfspr(949));
220 printf("\n%04x %08x ", 1019, mfspr(1019));
221 printf("\n%04x %08x ", 979, mfspr(979));
222 printf("\n%04x %08x ", 8, mfspr(8));
223 printf("\n%04x %08x ", 945, mfspr(945));
224 printf("\n%04x %08x ", 987, mfspr(987));
225 printf("\n%04x %08x ", 287, mfspr(287));
226 printf("\n%04x %08x ", 953, mfspr(953));
227 printf("\n%04x %08x ", 955, mfspr(955));
228 printf("\n%04x %08x ", 272, mfspr(272));
229 printf("\n%04x %08x ", 273, mfspr(273));
230 printf("\n%04x %08x ", 274, mfspr(274));
231 printf("\n%04x %08x ", 275, mfspr(275));
232 printf("\n%04x %08x ", 260, mfspr(260));
233 printf("\n%04x %08x ", 276, mfspr(276));
234 printf("\n%04x %08x ", 261, mfspr(261));
235 printf("\n%04x %08x ", 277, mfspr(277));
236 printf("\n%04x %08x ", 262, mfspr(262));
237 printf("\n%04x %08x ", 278, mfspr(278));
238 printf("\n%04x %08x ", 263, mfspr(263));
239 printf("\n%04x %08x ", 279, mfspr(279));
240 printf("\n%04x %08x ", 26, mfspr(26));
241 printf("\n%04x %08x ", 27, mfspr(27));
242 printf("\n%04x %08x ", 990, mfspr(990));
243 printf("\n%04x %08x ", 991, mfspr(991));
244 printf("\n%04x %08x ", 956, mfspr(956));
245 printf("\n%04x %08x ", 284, mfspr(284));
246 printf("\n%04x %08x ", 285, mfspr(285));
247 printf("\n%04x %08x ", 986, mfspr(986));
248 printf("\n%04x %08x ", 984, mfspr(984));
249 printf("\n%04x %08x ", 256, mfspr(256));
250 printf("\n%04x %08x ", 1, mfspr(1));
251 printf("\n%04x %08x ", 944, mfspr(944));
252 printf("\n");
253
254 return 0;
255}
256U_BOOT_CMD(
257 dumpspr, 1, 1, do_dumpspr,
Peter Tyser2fb26042009-01-27 18:03:12 -0600258 "Dump all SPR registers",
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200259 ""
stroeseaee2fa22004-12-16 18:17:50 +0000260);
261#endif