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wdenkba56f622004-02-06 23:19:44 +00001/*
Peter Tysere0299072009-07-17 19:01:07 -05002* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
wdenkba56f622004-02-06 23:19:44 +00003*
4* See file CREDITS for list of people who contributed to this
5* project.
6*
7* This program is free software; you can redistribute it and/or
8* modify it under the terms of the GNU General Public License as
9* published by the Free Software Foundation; either version 2 of
10* the License, or (at your option) any later version.
11*
12* This program is distributed in the hope that it will be useful,
13* but WITHOUT ANY WARRANTY; without even the implied warranty of
14* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15* GNU General Public License for more details.
16*
17* You should have received a copy of the GNU General Public License
18* along with this program; if not, write to the Free Software
19* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20* MA 02111-1307 USA
21*/
22
23#include <ppc_asm.tmpl>
Stefan Roesecf6eb6d2010-04-14 13:57:18 +020024#include <asm/mmu.h>
wdenkba56f622004-02-06 23:19:44 +000025#include <config.h>
Stefan Roese550650d2010-09-20 16:05:31 +020026#include <asm/ppc4xx.h>
wdenkba56f622004-02-06 23:19:44 +000027
Peter Tysere0299072009-07-17 19:01:07 -050028/*
wdenkba56f622004-02-06 23:19:44 +000029 * TLB TABLE
30 *
31 * This table is used by the cpu boot code to setup the initial tlb
32 * entries. Rather than make broad assumptions in the cpu source tree,
33 * this table lets each board set things up however they like.
34 *
Peter Tysere0299072009-07-17 19:01:07 -050035 * Pointer to the table is returned in r1
36 */
wdenkba56f622004-02-06 23:19:44 +000037
38 .section .bootpg,"ax"
39 .globl tlbtab
40
41tlbtab:
42 tlbtab_start
Stefan Roesecf6eb6d2010-04-14 13:57:18 +020043 tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
44 tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
45 tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX | SA_IG)
46 tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
47 tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_RWX | SA_IG )
48 tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
49 tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
wdenkba56f622004-02-06 23:19:44 +000050 tlbtab_end