blob: 363be97a59150571ceb00c67460b9a994e088d65 [file] [log] [blame]
wdenkdb01a2e2004-04-15 23:14:49 +00001/*
2 * Copyright (c) 2004 Picture Elements, Inc.
3 * Stephen Williams (steve@icarus.com)
4 *
5 * This source code is free software; you can redistribute it
6 * and/or modify it in source code form under the terms of the GNU
7 * General Public License as published by the Free Software
8 * Foundation; either version 2 of the License, or (at your option)
9 * any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
19 */
20#ident "$Id:$"
21
22# include <common.h>
23# include <pci.h>
24# include "jse_priv.h"
25
26/*
27 * The JSE board has an Intel 21555 non-transparent bridge for
28 * communication with the host. We need to render it harmless on the
29 * JSE side, but leave it alone on the host (primary) side. Normally,
30 * this will all be done before the host BIOS can gain access to the
31 * board, due to the Primary Access Lockout bit.
32 *
33 * The host_bridge_init function is called as a late initialization
34 * function, after most of the board is set up, including a PCI scan.
35 */
36
37void host_bridge_init (void)
38{
39 /* The bridge chip is at a fixed location. */
40 pci_dev_t dev = PCI_BDF (0, 10, 0);
41
wdenkcce625e2004-09-28 19:00:19 +000042 /* Set PCI Class code --
43 The primary side sees this class code at 0x08 in the
44 primary config space. This must be something other then a
45 bridge, or MS Windows starts doing weird stuff to me. */
46 pci_write_config_dword (dev, 0x48, 0x04800000);
wdenkdb01a2e2004-04-15 23:14:49 +000047
48 /* Set subsystem ID --
49 The primary side sees this value at 0x2c. We set it here so
50 that the host can tell what sort of device this is:
51 We are a Picture Elements [0x12c5] JSE [0x008a]. */
52 pci_write_config_dword (dev, 0x6c, 0x008a12c5);
53
54 /* Downstream (Primary-to-Secondary) BARs are set up mostly
55 off. We need only the Memory-0 Bar so that the host can get
56 at the CSR region to set up tables and the lot. */
57
58 /* Downstream Memory 0 setup (4K for CSR) */
59 pci_write_config_dword (dev, 0xac, 0xfffff000);
60 /* Downstream Memory 1 setup (off) */
61 pci_write_config_dword (dev, 0xb0, 0x00000000);
62 /* Downstream Memory 2 setup (off) */
63 pci_write_config_dword (dev, 0xb4, 0x00000000);
64 /* Downstream Memory 3 setup (off) */
65 pci_write_config_dword (dev, 0xb8, 0x00000000);
66
67 /* Upstream (Secondary-to-Primary) BARs are used to get at
68 host memory from the JSE card. Create two regions: a small
69 one to manage individual word reads/writes, and a larger
70 one for doing bulk frame moves. */
71
72 /* Upstream Memory 0 Setup -- (BAR2) 4K non-prefetchable */
73 pci_write_config_dword (dev, 0xc4, 0xfffff000);
74 /* Upstream Memory 1 setup -- (BAR3) 4K non-prefetchable */
75 pci_write_config_dword (dev, 0xc8, 0xfffff000);
76
77 /* Upstream Memory 2 (BAR4) uses page translation, and is set
78 up in CCR1. Configure for 4K pages. */
79
80 /* Set CCR1,0 reigsters. This clears the Primary PCI Lockout
81 bit as well, so we are done configuring after this
82 point. Therefore, this must be the last step.
83
84 CC1[15:12]= 0 (disable I2O message unit)
85 CC1[11:8] = 0x5 (4K page size)
86 CC0[11] = 1 (Secondary Clock Disable: disable clock)
87 CC0[10] = 0 (Primary Access Lockout: allow primary access)
88 */
89 pci_write_config_dword (dev, 0xcc, 0x05000800);
90}