blob: 8bc8342701cd7920b47d28bb9d2bef9977788fb9 [file] [log] [blame]
Andre Schwarz7fb3e7a2011-04-14 15:11:44 +02001/*
2 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
3 *
4 * Copyright (C) 2011 Matrix Vision GmbH
5 * Andre Schwarz <andre.schwarz@matrix-vision.de>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 */
15
16#include <common.h>
17#include <mpc83xx.h>
18#include <pci.h>
19#include <asm/io.h>
20#include <asm/fsl_mpc83xx_serdes.h>
21#include "mergerbox.h"
22#include "fpga.h"
23#include "../common/mv_common.h"
24
25static struct pci_region pci_regions[] = {
26 {
27 .bus_start = CONFIG_SYS_PCI_MEM_BASE,
28 .phys_start = CONFIG_SYS_PCI_MEM_PHYS,
29 .size = CONFIG_SYS_PCI_MEM_SIZE,
30 .flags = PCI_REGION_MEM | PCI_REGION_PREFETCH
31 },
32 {
33 .bus_start = CONFIG_SYS_PCI_MMIO_BASE,
34 .phys_start = CONFIG_SYS_PCI_MMIO_PHYS,
35 .size = CONFIG_SYS_PCI_MMIO_SIZE,
36 .flags = PCI_REGION_MEM
37 },
38 {
39 .bus_start = CONFIG_SYS_PCI_IO_BASE,
40 .phys_start = CONFIG_SYS_PCI_IO_PHYS,
41 .size = CONFIG_SYS_PCI_IO_SIZE,
42 .flags = PCI_REGION_IO
43 }
44};
45
46static struct pci_region pcie_regions_0[] = {
47 {
48 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
49 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
50 .size = CONFIG_SYS_PCIE1_MEM_SIZE,
51 .flags = PCI_REGION_MEM,
52 },
53 {
54 .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
55 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
56 .size = CONFIG_SYS_PCIE1_IO_SIZE,
57 .flags = PCI_REGION_IO,
58 },
59};
60
61static struct pci_region pcie_regions_1[] = {
62 {
63 .bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
64 .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
65 .size = CONFIG_SYS_PCIE2_MEM_SIZE,
66 .flags = PCI_REGION_MEM,
67 },
68 {
69 .bus_start = CONFIG_SYS_PCIE2_IO_BASE,
70 .phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
71 .size = CONFIG_SYS_PCIE2_IO_SIZE,
72 .flags = PCI_REGION_IO,
73 },
74};
75
76void pci_init_board(void)
77{
78 volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
79 volatile sysconf83xx_t *sysconf = &immr->sysconf;
80 volatile clk83xx_t *clk = (clk83xx_t *)&immr->clk;
81 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
82 volatile law83xx_t *pcie_law = sysconf->pcielaw;
83 struct pci_region *reg[] = { pci_regions };
84 struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
85
86 volatile gpio83xx_t *gpio;
87 gpio = (gpio83xx_t *)&immr->gpio[0];
88
89 gpio->dat = MV_GPIO1_DAT;
90 gpio->odr = MV_GPIO1_ODE;
91 gpio->dir = MV_GPIO1_OUT;
92
93 gpio = (gpio83xx_t *)&immr->gpio[1];
94
95 gpio->dat = MV_GPIO2_DAT;
96 gpio->odr = MV_GPIO2_ODE;
97 gpio->dir = MV_GPIO2_OUT;
98
99 printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh,
100 immr->sysconf.sicrl);
101
102 /* Enable PCI_CLK[0:1] */
103 clk->occr |= 0xc0000000;
104 udelay(2000);
105
106 mergerbox_init_fpga();
107 mv_load_fpga();
108
109 mergerbox_tft_dim(0);
110
111 /* Configure PCI Local Access Windows */
112 pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
113 pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
114
115 pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
116 pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
117
118 udelay(2000);
119
120 mpc83xx_pci_init(1, reg);
121
122 /* Deassert the resets in the control register */
123 out_be32(&sysconf->pecr1, 0xE0008000);
124 out_be32(&sysconf->pecr2, 0xE0008000);
125 udelay(2000);
126
127 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
128 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
129
130 out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
131 out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
132
133 mpc83xx_pcie_init(2, pcie_reg);
134}