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Tom Rini4549e782018-05-06 18:27:01 -04001/* SPDX-License-Identifier: GPL-2.0 OR IBM-pibs */
Wolfgang Denk46263f22013-07-28 22:12:45 +02002/*
Wolfgang Denk46263f22013-07-28 22:12:45 +02003 * Additions (C) Copyright 2009 Industrie Dial Face S.p.A.
4 */
wdenk214ec6b2001-10-08 19:18:17 +00005/*----------------------------------------------------------------------------+
6|
wdenk65bd0e22003-09-18 10:45:21 +00007| File Name: miiphy.h
wdenk214ec6b2001-10-08 19:18:17 +00008|
wdenk65bd0e22003-09-18 10:45:21 +00009| Function: Include file defining PHY registers.
wdenk214ec6b2001-10-08 19:18:17 +000010|
wdenk65bd0e22003-09-18 10:45:21 +000011| Author: Mark Wisner
wdenk214ec6b2001-10-08 19:18:17 +000012|
wdenk214ec6b2001-10-08 19:18:17 +000013+----------------------------------------------------------------------------*/
14#ifndef _miiphy_h_
15#define _miiphy_h_
16
Andy Fleming5f184712011-04-08 02:10:27 -050017#include <common.h>
Mike Frysinger8ef583a2010-12-23 15:40:12 -050018#include <linux/mii.h>
Andy Fleming5f184712011-04-08 02:10:27 -050019#include <linux/list.h>
Marian Balakowicz63ff0042005-10-28 22:30:33 +020020#include <net.h>
Andy Fleming5f184712011-04-08 02:10:27 -050021#include <phy.h>
22
Wolfgang Denkf915c932011-12-07 08:35:14 +010023int miiphy_read(const char *devname, unsigned char addr, unsigned char reg,
Larry Johnson298035d2007-10-31 11:21:29 -050024 unsigned short *value);
Wolfgang Denkf915c932011-12-07 08:35:14 +010025int miiphy_write(const char *devname, unsigned char addr, unsigned char reg,
Larry Johnson298035d2007-10-31 11:21:29 -050026 unsigned short value);
Andy Fleming16a53232011-04-07 14:38:35 -050027int miiphy_info(const char *devname, unsigned char addr, unsigned int *oui,
Larry Johnson298035d2007-10-31 11:21:29 -050028 unsigned char *model, unsigned char *rev);
Andy Fleming16a53232011-04-07 14:38:35 -050029int miiphy_reset(const char *devname, unsigned char addr);
30int miiphy_speed(const char *devname, unsigned char addr);
31int miiphy_duplex(const char *devname, unsigned char addr);
32int miiphy_is_1000base_x(const char *devname, unsigned char addr);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020033#ifdef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
Andy Fleming16a53232011-04-07 14:38:35 -050034int miiphy_link(const char *devname, unsigned char addr);
wdenkfc3e2162003-10-08 22:33:00 +000035#endif
wdenk214ec6b2001-10-08 19:18:17 +000036
Andy Fleming16a53232011-04-07 14:38:35 -050037void miiphy_init(void);
Marian Balakowiczd9785c12005-11-30 18:06:04 +010038
Andy Fleming16a53232011-04-07 14:38:35 -050039int miiphy_set_current_dev(const char *devname);
40const char *miiphy_get_current_dev(void);
Andy Fleming5f184712011-04-08 02:10:27 -050041struct mii_dev *mdio_get_current_dev(void);
42struct mii_dev *miiphy_get_dev_by_name(const char *devname);
43struct phy_device *mdio_phydev_for_ethname(const char *devname);
Marian Balakowicz63ff0042005-10-28 22:30:33 +020044
Andy Fleming16a53232011-04-07 14:38:35 -050045void miiphy_listdev(void);
Marian Balakowicz63ff0042005-10-28 22:30:33 +020046
Andy Fleming5f184712011-04-08 02:10:27 -050047struct mii_dev *mdio_alloc(void);
Bin Mengcb6baca2015-10-07 21:32:37 -070048void mdio_free(struct mii_dev *bus);
Andy Fleming5f184712011-04-08 02:10:27 -050049int mdio_register(struct mii_dev *bus);
Michal Simek79e2a6a2016-12-08 10:06:26 +010050
51/**
52 * mdio_register_seq - Register mdio bus with sequence number
53 * @bus: mii device structure
54 * @seq: sequence number
55 *
56 * Return: 0 if success, negative value if error
57 */
58int mdio_register_seq(struct mii_dev *bus, int seq);
Bin Mengcb6baca2015-10-07 21:32:37 -070059int mdio_unregister(struct mii_dev *bus);
Andy Fleming5f184712011-04-08 02:10:27 -050060void mdio_list_devices(void);
61
Luigi 'Comio' Mantellini4ba31ab2009-10-10 12:42:20 +020062#ifdef CONFIG_BITBANGMII
Marian Balakowicz63ff0042005-10-28 22:30:33 +020063
Luigi 'Comio' Mantellini4ba31ab2009-10-10 12:42:20 +020064#define BB_MII_DEVNAME "bb_miiphy"
65
66struct bb_miiphy_bus {
Mike Frysingerf6add132011-11-10 14:11:04 +000067 char name[16];
Luigi 'Comio' Mantellini4ba31ab2009-10-10 12:42:20 +020068 int (*init)(struct bb_miiphy_bus *bus);
69 int (*mdio_active)(struct bb_miiphy_bus *bus);
70 int (*mdio_tristate)(struct bb_miiphy_bus *bus);
71 int (*set_mdio)(struct bb_miiphy_bus *bus, int v);
72 int (*get_mdio)(struct bb_miiphy_bus *bus, int *v);
73 int (*set_mdc)(struct bb_miiphy_bus *bus, int v);
74 int (*delay)(struct bb_miiphy_bus *bus);
75#ifdef CONFIG_BITBANGMII_MULTI
76 void *priv;
77#endif
78};
79
80extern struct bb_miiphy_bus bb_miiphy_buses[];
81extern int bb_miiphy_buses_num;
82
Andy Fleming16a53232011-04-07 14:38:35 -050083void bb_miiphy_init(void);
Joe Hershbergerdfcc4962016-08-08 11:28:39 -050084int bb_miiphy_read(struct mii_dev *miidev, int addr, int devad, int reg);
85int bb_miiphy_write(struct mii_dev *miidev, int addr, int devad, int reg,
86 u16 value);
Luigi 'Comio' Mantellini4ba31ab2009-10-10 12:42:20 +020087#endif
wdenk214ec6b2001-10-08 19:18:17 +000088
89/* phy seed setup */
wdenk65bd0e22003-09-18 10:45:21 +000090#define AUTO 99
Larry Johnson298035d2007-10-31 11:21:29 -050091#define _1000BASET 1000
wdenk65bd0e22003-09-18 10:45:21 +000092#define _100BASET 100
93#define _10BASET 10
94#define HALF 22
95#define FULL 44
wdenk214ec6b2001-10-08 19:18:17 +000096
97/* phy register offsets */
Mike Frysinger8ef583a2010-12-23 15:40:12 -050098#define MII_MIPSCR 0x11
wdenk214ec6b2001-10-08 19:18:17 +000099
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500100/* MII_LPA */
Larry Johnson298035d2007-10-31 11:21:29 -0500101#define PHY_ANLPAR_PSB_802_3 0x0001
102#define PHY_ANLPAR_PSB_802_9 0x0002
wdenkb9711de2004-04-25 13:18:40 +0000103
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500104/* MII_CTRL1000 masks */
Larry Johnson71bc6e62007-11-01 08:46:50 -0500105#define PHY_1000BTCR_1000FD 0x0200
106#define PHY_1000BTCR_1000HD 0x0100
107
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500108/* MII_STAT1000 masks */
Larry Johnson298035d2007-10-31 11:21:29 -0500109#define PHY_1000BTSR_MSCF 0x8000
110#define PHY_1000BTSR_MSCR 0x4000
111#define PHY_1000BTSR_LRS 0x2000
112#define PHY_1000BTSR_RRS 0x1000
113#define PHY_1000BTSR_1000FD 0x0800
114#define PHY_1000BTSR_1000HD 0x0400
wdenk855a4962004-03-14 18:23:55 +0000115
Larry Johnson71bc6e62007-11-01 08:46:50 -0500116/* phy EXSR */
Mike Frysinger8ef583a2010-12-23 15:40:12 -0500117#define ESTATUS_1000XF 0x8000
118#define ESTATUS_1000XH 0x4000
Larry Johnson71bc6e62007-11-01 08:46:50 -0500119
wdenk214ec6b2001-10-08 19:18:17 +0000120#endif