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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkc6097192002-11-03 00:24:07 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_405GP 1 /* This is a PPC405 CPU */
wdenkc837dcb2004-01-20 23:12:12 +000021#define CONFIG_OCRTC 1 /* ...on a OCRTC board */
wdenkc6097192002-11-03 00:24:07 +000022
Wolfgang Denk2ae18242010-10-06 09:05:45 +020023#define CONFIG_SYS_TEXT_BASE 0xFFFD0000
24
wdenkc837dcb2004-01-20 23:12:12 +000025#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
wdenkc6097192002-11-03 00:24:07 +000026
wdenkc837dcb2004-01-20 23:12:12 +000027#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
wdenkc6097192002-11-03 00:24:07 +000028
29#define CONFIG_BAUDRATE 9600
30#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
31
32#undef CONFIG_BOOTARGS
33#define CONFIG_BOOTCOMMAND "go fff00100"
34
35#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020036#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenkc6097192002-11-03 00:24:07 +000037
Ben Warren96e21f82008-10-27 23:50:15 -070038#define CONFIG_PPC4xx_EMAC
wdenkc6097192002-11-03 00:24:07 +000039#define CONFIG_MII 1 /* MII PHY management */
wdenkc837dcb2004-01-20 23:12:12 +000040#define CONFIG_PHY_ADDR 0 /* PHY address */
stroesea20b27a2004-12-16 18:05:42 +000041#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
wdenkc6097192002-11-03 00:24:07 +000042
Jon Loeligere18a1062007-07-08 14:21:43 -050043
44/*
Jon Loeliger659e2f62007-07-10 09:10:49 -050045 * BOOTP options
46 */
47#define CONFIG_BOOTP_BOOTFILESIZE
48#define CONFIG_BOOTP_BOOTPATH
49#define CONFIG_BOOTP_GATEWAY
50#define CONFIG_BOOTP_HOSTNAME
51
52
53/*
Jon Loeligere18a1062007-07-08 14:21:43 -050054 * Command line configuration.
55 */
56#include <config_cmd_default.h>
57
58#define CONFIG_CMD_PCI
59#define CONFIG_CMD_IRQ
60#define CONFIG_CMD_ASKENV
61#define CONFIG_CMD_ELF
62#define CONFIG_CMD_BSP
63#define CONFIG_CMD_EEPROM
64
wdenkc6097192002-11-03 00:24:07 +000065
66#define CONFIG_MAC_PARTITION
67#define CONFIG_DOS_PARTITION
68
wdenkc837dcb2004-01-20 23:12:12 +000069#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenkc6097192002-11-03 00:24:07 +000070
wdenkc837dcb2004-01-20 23:12:12 +000071#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
wdenkc6097192002-11-03 00:24:07 +000072
73/*
74 * Miscellaneous configurable options
75 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jon Loeligere18a1062007-07-08 14:21:43 -050077#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +000079#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkc6097192002-11-03 00:24:07 +000081#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
83#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
84#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkc6097192002-11-03 00:24:07 +000085
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
wdenkc6097192002-11-03 00:24:07 +000087
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
89#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkc6097192002-11-03 00:24:07 +000090
Stefan Roese550650d2010-09-20 16:05:31 +020091#define CONFIG_CONS_INDEX 1 /* Use UART0 */
92#define CONFIG_SYS_NS16550
93#define CONFIG_SYS_NS16550_SERIAL
94#define CONFIG_SYS_NS16550_REG_SIZE 1
95#define CONFIG_SYS_NS16550_CLK get_serial_clock()
96
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_BASE_BAUD 691200
wdenkc6097192002-11-03 00:24:07 +000099
100/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk8bde7f72003-06-27 21:31:46 +0000102 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
103 57600, 115200, 230400, 460800, 921600 }
wdenkc6097192002-11-03 00:24:07 +0000104
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
106#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
wdenkc6097192002-11-03 00:24:07 +0000107
wdenkc6097192002-11-03 00:24:07 +0000108#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
109
110/*-----------------------------------------------------------------------
111 * PCI stuff
112 *-----------------------------------------------------------------------
113 */
wdenkc837dcb2004-01-20 23:12:12 +0000114#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
115#define PCI_HOST_FORCE 1 /* configure as pci host */
116#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
wdenkc6097192002-11-03 00:24:07 +0000117
wdenkc837dcb2004-01-20 23:12:12 +0000118#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000119#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
wdenkc837dcb2004-01-20 23:12:12 +0000120#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
121#define CONFIG_PCI_PNP /* do pci plug-and-play */
122 /* resource configuration */
wdenkc6097192002-11-03 00:24:07 +0000123
wdenkc837dcb2004-01-20 23:12:12 +0000124#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
wdenkc6097192002-11-03 00:24:07 +0000125
stroesea20b27a2004-12-16 18:05:42 +0000126#define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/
stroesead10dd92003-02-14 11:21:23 +0000127
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
129#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0410 /* PCI Device ID: OCRTC */
130#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
131#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
132#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
133#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
134#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
135#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
136#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
wdenkc6097192002-11-03 00:24:07 +0000137
138/*-----------------------------------------------------------------------
139 * Start addresses for the final memory configuration
140 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkc6097192002-11-03 00:24:07 +0000142 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_SDRAM_BASE 0x00000000
144#define CONFIG_SYS_FLASH_BASE 0xFFFD0000
145#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
146#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */
147#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
wdenkc6097192002-11-03 00:24:07 +0000148
149/*
150 * For booting Linux, the board info and command line data
151 * have to be in the first 8 MB of memory, since this is
152 * the maximum mapped by the Linux kernel during initialization.
153 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc6097192002-11-03 00:24:07 +0000155/*-----------------------------------------------------------------------
156 * FLASH organization
157 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
159#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenkc6097192002-11-03 00:24:07 +0000160
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
162#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkc6097192002-11-03 00:24:07 +0000163
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
165#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
166#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
wdenkc6097192002-11-03 00:24:07 +0000167/*
168 * The following defines are added for buggy IOP480 byte interface.
169 * All other boards should use the standard values (CPCI405 etc.)
170 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
172#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
173#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
wdenkc6097192002-11-03 00:24:07 +0000174
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
wdenkc6097192002-11-03 00:24:07 +0000176
177#if 0 /* Use NVRAM for environment variables */
178/*-----------------------------------------------------------------------
179 * NVRAM organization
180 */
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200181#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */
183#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200184#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
185#define CONFIG_ENV_ADDR \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
187#define CONFIG_SYS_NVRAM_VXWORKS_OFFS 0x6900 /* Offset for VxWorks eth-addr */
wdenkc6097192002-11-03 00:24:07 +0000188
189#else /* Use EEPROM for environment variables */
190
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200191#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200192#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
193#define CONFIG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */
wdenk8bde7f72003-06-27 21:31:46 +0000194 /* total size of a CAT24WC08 is 1024 bytes */
wdenkc6097192002-11-03 00:24:07 +0000195#endif
196
197/*-----------------------------------------------------------------------
198 * I2C EEPROM (CAT24WC08) for environment
199 */
Dirk Eibach880540d2013-04-25 02:40:01 +0000200#define CONFIG_SYS_I2C
201#define CONFIG_SYS_I2C_PPC4XX
202#define CONFIG_SYS_I2C_PPC4XX_CH0
203#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
204#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
wdenkc6097192002-11-03 00:24:07 +0000205
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
207#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
wdenkc837dcb2004-01-20 23:12:12 +0000208/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
210#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
wdenkc6097192002-11-03 00:24:07 +0000211 /* 16 byte page write mode using*/
wdenkc837dcb2004-01-20 23:12:12 +0000212 /* last 4 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
wdenkc6097192002-11-03 00:24:07 +0000214
wdenkc6097192002-11-03 00:24:07 +0000215/*
216 * Init Memory Controller:
217 *
218 * BR0/1 and OR0/1 (FLASH)
219 */
220
221#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
222#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */
223
224/*-----------------------------------------------------------------------
225 * External Bus Controller (EBC) Setup
226 */
227
wdenkc837dcb2004-01-20 23:12:12 +0000228/* Memory Bank 0 (Flash Bank 0) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_EBC_PB0AP 0x92015480
230#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000231
wdenkc837dcb2004-01-20 23:12:12 +0000232/* Memory Bank 1 (Flash Bank 1) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_EBC_PB1AP 0x92015480
234#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
wdenkc6097192002-11-03 00:24:07 +0000235
wdenkc837dcb2004-01-20 23:12:12 +0000236/* Memory Bank 2 (PLD - FPGA-boot) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_EBC_PB2AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
wdenk8bde7f72003-06-27 21:31:46 +0000238 /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
wdenkc6097192002-11-03 00:24:07 +0000240
wdenkc837dcb2004-01-20 23:12:12 +0000241/* Memory Bank 3 (PLD - OSL) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_EBC_PB3AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
wdenk8bde7f72003-06-27 21:31:46 +0000243 /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_EBC_PB3CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
wdenkc6097192002-11-03 00:24:07 +0000245
wdenkc837dcb2004-01-20 23:12:12 +0000246/* Memory Bank 4 (Spartan2 1) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_EBC_PB4AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
wdenk8bde7f72003-06-27 21:31:46 +0000248 /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_EBC_PB4CR 0xF209C000 /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/
wdenkc6097192002-11-03 00:24:07 +0000250
wdenkc837dcb2004-01-20 23:12:12 +0000251/* Memory Bank 5 (Spartan2 2) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_EBC_PB5AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
wdenk8bde7f72003-06-27 21:31:46 +0000253 /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_EBC_PB5CR 0xF309C000 /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/
wdenkc6097192002-11-03 00:24:07 +0000255
wdenkc837dcb2004-01-20 23:12:12 +0000256/* Memory Bank 6 (Virtex 1) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_EBC_PB6AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
wdenk8bde7f72003-06-27 21:31:46 +0000258 /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_EBC_PB6CR 0xF409A000 /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/
wdenkc6097192002-11-03 00:24:07 +0000260
wdenkc837dcb2004-01-20 23:12:12 +0000261/* Memory Bank 7 (Virtex 2) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_EBC_PB7AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
wdenk8bde7f72003-06-27 21:31:46 +0000263 /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_EBC_PB7CR 0xF509A000 /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/
wdenkc6097192002-11-03 00:24:07 +0000265
266
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
wdenkc6097192002-11-03 00:24:07 +0000268
269/*-----------------------------------------------------------------------
270 * Definitions for initial stack pointer and data area (in DPRAM)
271 */
272
273/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_TEMP_STACK_OCM 1
wdenkc6097192002-11-03 00:24:07 +0000275
276/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
278#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
wdenkc6097192002-11-03 00:24:07 +0000279
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200281#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200282#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkc6097192002-11-03 00:24:07 +0000284
wdenkc6097192002-11-03 00:24:07 +0000285#endif /* __CONFIG_H */