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wdenkb6e4c402004-01-02 16:05:07 +00001/*
2 * (C) Copyright 2003
3 * Denis Peter d.peter@mpl.ch
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkb6e4c402004-01-02 16:05:07 +00006 */
7
8/*
9 * File: PATI.h
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 */
18
19#define CONFIG_MPC555 1 /* This is an MPC555 CPU */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020020#define CONFIG_PATI 1 /* ...On a PATI board */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020021
22#define CONFIG_SYS_TEXT_BASE 0xFFF00000
23
David Müller (ELSOFT AG)6c4c9a72014-09-30 12:32:23 +020024#define CONFIG_SYS_GENERIC_BOARD
25
wdenkb6e4c402004-01-02 16:05:07 +000026/* Serial Console Configuration */
27#define CONFIG_5xx_CONS_SCI1
28#undef CONFIG_5xx_CONS_SCI2
29
30#define CONFIG_BAUDRATE 9600
31
wdenkb6e4c402004-01-02 16:05:07 +000032
Jon Loeligeracf02692007-07-08 14:49:44 -050033/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -050034 * BOOTP options
35 */
36#define CONFIG_BOOTP_BOOTFILESIZE
37#define CONFIG_BOOTP_BOOTPATH
38#define CONFIG_BOOTP_GATEWAY
39#define CONFIG_BOOTP_HOSTNAME
40
41
42/*
Jon Loeligeracf02692007-07-08 14:49:44 -050043 * Command line configuration.
44 */
45#define CONFIG_CMD_MEMORY
46#define CONFIG_CMD_LOADB
47#define CONFIG_CMD_REGINFO
48#define CONFIG_CMD_FLASH
49#define CONFIG_CMD_LOADS
Mike Frysingerbdab39d2009-01-28 19:08:14 -050050#define CONFIG_CMD_SAVEENV
Jon Loeligeracf02692007-07-08 14:49:44 -050051#define CONFIG_CMD_REGINFO
52#define CONFIG_CMD_BDI
53#define CONFIG_CMD_CONSOLE
54#define CONFIG_CMD_RUN
55#define CONFIG_CMD_BSP
56#define CONFIG_CMD_IMI
57#define CONFIG_CMD_EEPROM
58#define CONFIG_CMD_IRQ
59#define CONFIG_CMD_MISC
60
wdenkb6e4c402004-01-02 16:05:07 +000061
62#if 0
63#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
64#else
65#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
66#endif
Wolfgang Denk53677ef2008-05-20 16:00:29 +020067#define CONFIG_BOOTCOMMAND "" /* autoboot command */
wdenkb6e4c402004-01-02 16:05:07 +000068
69#define CONFIG_BOOTARGS "" /* */
70
Wolfgang Denk53677ef2008-05-20 16:00:29 +020071#define CONFIG_WATCHDOG /* turn on platform specific watchdog */
wdenkb6e4c402004-01-02 16:05:07 +000072
wdenk3a473b22004-01-03 00:43:19 +000073/*#define CONFIG_STATUS_LED 1 */ /* Enable status led */
wdenkb6e4c402004-01-02 16:05:07 +000074
75#define CONFIG_LOADS_ECHO 1 /* Echo on for serial download */
76
77/*
78 * Miscellaneous configurable options
79 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */
wdenkb6e4c402004-01-02 16:05:07 +000081#define CONFIG_PREBOOT
82
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083#define CONFIG_SYS_LONGHELP /* undef to save memory */
84#define CONFIG_SYS_PROMPT "pati=> " /* Monitor Command Prompt */
Jon Loeligeracf02692007-07-08 14:49:44 -050085#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkb6e4c402004-01-02 16:05:07 +000087#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkb6e4c402004-01-02 16:05:07 +000089#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
91#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
92#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkb6e4c402004-01-02 16:05:07 +000093
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#define CONFIG_SYS_MEMTEST_START 0x00010000 /* memtest works on */
95#define CONFIG_SYS_MEMTEST_END 0x00A00000 /* 10 MB in SRAM */
wdenkb6e4c402004-01-02 16:05:07 +000096
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkb6e4c402004-01-02 16:05:07 +000098
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 1250000 }
wdenkb6e4c402004-01-02 16:05:07 +0000100
David Müller (ELSOFT AG)cf7d4502014-09-30 13:23:54 +0200101#define CONFIG_BOARD_EARLY_INIT_F
wdenkb6e4c402004-01-02 16:05:07 +0000102
103/***********************************************************************
104 * Last Stage Init
105 ***********************************************************************/
106#define CONFIG_LAST_STAGE_INIT
107
108/*
109 * Low Level Configuration Settings
110 */
111
112/*
113 * Internal Memory Mapped (This is not the IMMR content)
114 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_IMMR 0x01C00000 /* Physical start adress of internal memory map */
wdenkb6e4c402004-01-02 16:05:07 +0000116
117/*
118 * Definitions for initial stack pointer and data area
119 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x003f9800) /* Physical start adress of internal MPC555 writable RAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200121#define CONFIG_SYS_INIT_RAM_SIZE (CONFIG_SYS_IMMR + 0x003fffff) /* Physical end adress of internal MPC555 used RAM area */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200122#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_RAM_ADDR) - GENERATED_GBL_DATA_SIZE) /* Offset from the beginning of ram */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_IMMR + 0x03fa000) /* Physical start adress of inital stack */
wdenkb6e4c402004-01-02 16:05:07 +0000124/*
125 * Start addresses for the final memory configuration
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkb6e4c402004-01-02 16:05:07 +0000127 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* Monitor won't change memory map */
129#define CONFIG_SYS_FLASH_BASE 0xffC00000 /* External flash */
wdenkb6e4c402004-01-02 16:05:07 +0000130#define PCI_BASE 0x03000000 /* PCI Base (CS2) */
131#define PCI_CONFIG_BASE 0x04000000 /* PCI & PLD (CS3) */
132#define PLD_CONFIG_BASE 0x04001000 /* PLD (CS3) */
133
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_MONITOR_BASE 0xFFF00000
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200135/* CONFIG_SYS_FLASH_BASE */ /* CONFIG_SYS_TEXT_BASE is defined in the board config.mk file. */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200136 /* This adress is given to the linker with -Ttext to */
137 /* locate the text section at this adress. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 192 kB for Monitor */
139#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkb6e4c402004-01-02 16:05:07 +0000140
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_RESET_ADDRESS (PLD_CONFIG_BASE + 0x10) /* Adress which causes reset */
wdenkb6e4c402004-01-02 16:05:07 +0000142
143/*
144 * For booting Linux, the board info and command line data
145 * have to be in the first 8 MB of memory, since this is
146 * the maximum mapped by the Linux kernel during initialization.
147 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkb6e4c402004-01-02 16:05:07 +0000149
150
151/*-----------------------------------------------------------------------
152 * FLASH organization
153 *-----------------------------------------------------------------------
154 *
155 */
156
David Müllerd49f5b12011-12-22 13:38:22 +0100157#define CONFIG_SYS_FLASH_PROTECTION
158#define CONFIG_SYS_FLASH_EMPTY_INFO
wdenkb6e4c402004-01-02 16:05:07 +0000159
David Müllerd49f5b12011-12-22 13:38:22 +0100160#define CONFIG_SYS_FLASH_CFI
161#define CONFIG_FLASH_CFI_DRIVER
162
163#define CONFIG_FLASH_SHOW_PROGRESS 45
164
165#define CONFIG_SYS_MAX_FLASH_BANKS 1
166#define CONFIG_SYS_MAX_FLASH_SECT 128
wdenkb6e4c402004-01-02 16:05:07 +0000167
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200168#define CONFIG_ENV_IS_IN_EEPROM
169#ifdef CONFIG_ENV_IS_IN_EEPROM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200170#define CONFIG_ENV_OFFSET 0
171#define CONFIG_ENV_SIZE 2048
wdenkb6e4c402004-01-02 16:05:07 +0000172#endif
173
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200174#undef CONFIG_ENV_IS_IN_FLASH
175#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200176#define CONFIG_ENV_SIZE 0x00002000 /* Set whole sector as env */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_ENV_OFFSET ((0 - CONFIG_SYS_FLASH_BASE) - CONFIG_ENV_SIZE) /* Environment starts at this adress */
wdenkb6e4c402004-01-02 16:05:07 +0000178#endif
179
180
181#define CONFIG_SPI 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_SPI_CS_USED 0x09 /* CS0 and CS3 are used */
183#define CONFIG_SYS_SPI_CS_BASE 0x08 /* CS3 is active low */
184#define CONFIG_SYS_SPI_CS_ACT 0x00 /* CS3 is active low */
wdenkb6e4c402004-01-02 16:05:07 +0000185/*-----------------------------------------------------------------------
186 * SYPCR - System Protection Control
187 * SYPCR can only be written once after reset!
188 *-----------------------------------------------------------------------
189 * SW Watchdog freeze
190 */
191#undef CONFIG_WATCHDOG
192#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenkb6e4c402004-01-02 16:05:07 +0000194 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
195#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenkb6e4c402004-01-02 16:05:07 +0000197 SYPCR_SWP)
198#endif /* CONFIG_WATCHDOG */
199
wdenkb6e4c402004-01-02 16:05:07 +0000200/*-----------------------------------------------------------------------
201 * TBSCR - Time Base Status and Control
202 *-----------------------------------------------------------------------
203 * Clear Reference Interrupt Status, Timebase freezing enabled
204 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenkb6e4c402004-01-02 16:05:07 +0000206
207/*-----------------------------------------------------------------------
208 * PISCR - Periodic Interrupt Status and Control
209 *-----------------------------------------------------------------------
210 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
211 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenkb6e4c402004-01-02 16:05:07 +0000213
214/*-----------------------------------------------------------------------
215 * SCCR - System Clock and reset Control Register
216 *-----------------------------------------------------------------------
217 * Set clock output, timebase and RTC source and divider,
218 * power management and some other internal clocks
219 */
220#define SCCR_MASK SCCR_EBDF00
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_RTDIV | SCCR_RTSEL | \
wdenkb6e4c402004-01-02 16:05:07 +0000222 SCCR_COM01 | SCCR_DFNL000 | SCCR_DFNH000)
223
224/*-----------------------------------------------------------------------
225 * SIUMCR - SIU Module Configuration
226 *-----------------------------------------------------------------------
227 * Data show cycle
228 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_EARB | SIUMCR_GPC01 | SIUMCR_MLRC11) /* Disable data show cycle */
wdenkb6e4c402004-01-02 16:05:07 +0000230
231/*-----------------------------------------------------------------------
232 * PLPRCR - PLL, Low-Power, and Reset Control Register
233 *-----------------------------------------------------------------------
234 * Set all bits to 40 Mhz
235 *
236 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_OSC_CLK ((uint)4000000) /* Oscillator clock is 4MHz */
wdenkb6e4c402004-01-02 16:05:07 +0000238
239
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_PLPRCR (PLPRCR_MF_9 | PLPRCR_DIVF_0)
wdenkb6e4c402004-01-02 16:05:07 +0000241
242/*-----------------------------------------------------------------------
243 * UMCR - UIMB Module Configuration Register
244 *-----------------------------------------------------------------------
245 *
246 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_UMCR (UMCR_FSPEED) /* IMB clock same as U-bus */
wdenkb6e4c402004-01-02 16:05:07 +0000248
249/*-----------------------------------------------------------------------
250 * ICTRL - I-Bus Support Control Register
251 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_ICTRL (ICTRL_ISCT_SER_7) /* Take out of serialized mode */
wdenkb6e4c402004-01-02 16:05:07 +0000253
254/*-----------------------------------------------------------------------
255 * USIU - Memory Controller Register
256 *-----------------------------------------------------------------------
257 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_V | BR_BI | BR_PS_16 | BR_SETA)
259#define CONFIG_SYS_OR0_PRELIM (0xffc00000) /* SCY is not used if external TA is set */
wdenkb6e4c402004-01-02 16:05:07 +0000260/* SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_SDRAM_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
262#define CONFIG_SYS_OR1_PRELIM (OR_ADDR_MK_FF) /* SCY is not used if external TA is set */
wdenkb6e4c402004-01-02 16:05:07 +0000263/* PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_BR2_PRELIM (PCI_BASE | BR_V | BR_PS_32 | BR_SETA)
265#define CONFIG_SYS_OR2_PRELIM (OR_ADDR_MK_FF)
wdenkb6e4c402004-01-02 16:05:07 +0000266/* config registers: */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_BR3_PRELIM (PCI_CONFIG_BASE | BR_V | BR_BI | BR_PS_32 | BR_SETA)
268#define CONFIG_SYS_OR3_PRELIM (0xffff0000)
wdenkb6e4c402004-01-02 16:05:07 +0000269
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* We don't realign the flash */
wdenkb6e4c402004-01-02 16:05:07 +0000271
272/*-----------------------------------------------------------------------
273 * DER - Timer Decrementer
274 *-----------------------------------------------------------------------
275 * Initialise to zero
276 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_DER 0x00000000
wdenkb6e4c402004-01-02 16:05:07 +0000278
wdenkb6e4c402004-01-02 16:05:07 +0000279#define VERSION_TAG "released"
280#define CONFIG_ISO_STRING "MEV-10084-001"
281
282#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
283
284#endif /* __CONFIG_H */