blob: 5f30279fe66c50b89ec683c1ff43de640f2bca77 [file] [log] [blame]
Heiko Schocher4dd83492011-11-01 20:00:35 +00001/*
2 * Copyright (C) 2009 Texas Instruments Incorporated
3 *
4 * Copyright (C) 2011
5 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
6 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
Heiko Schocher4dd83492011-11-01 20:00:35 +00008 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */
14#define CONFIG_SYS_CONSOLE_INFO_QUIET
15
16/* SoC Configuration */
17#define CONFIG_ARM926EJS /* arm926ejs CPU */
18#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */
19#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */
Heiko Schocher4dd83492011-11-01 20:00:35 +000020#define CONFIG_SOC_DM365
21
22#define CONFIG_MACH_TYPE MACH_TYPE_DAVINCI_DM365_EVM
23
24#define CONFIG_HOSTNAME cam_enc_4xx
25
Nobuhiro Iwamatsu8913e6b2012-04-17 16:42:22 +000026#define CONFIG_BOARD_LATE_INIT
Heiko Schocher4dd83492011-11-01 20:00:35 +000027#define CONFIG_CAM_ENC_LED_MASK 0x0fc00000
28
29/* Memory Info */
30#define CONFIG_NR_DRAM_BANKS 1
31#define PHYS_SDRAM_1 0x80000000
32#define PHYS_SDRAM_1_SIZE (256 << 20) /* 256 MiB */
33#define DDR_4BANKS /* 4-bank DDR2 (256MB) */
34#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MB */
35#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
36
37/* Serial Driver info: UART0 for console */
38#define CONFIG_SYS_NS16550
39#define CONFIG_SYS_NS16550_SERIAL
40#define CONFIG_SYS_NS16550_REG_SIZE -4
41#define CONFIG_SYS_NS16550_COM1 0x01c20000
42#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK
Heiko Schocher4dd83492011-11-01 20:00:35 +000043#define CONFIG_CONS_INDEX 1
44#define CONFIG_BAUDRATE 115200
45
46/* Network Configuration */
47#define CONFIG_DRIVER_TI_EMAC
48#define CONFIG_EMAC_MDIO_PHY_NUM 0
49#define CONFIG_SYS_EMAC_TI_CLKDIV 0xa9 /* 1MHz */
50#define CONFIG_MII
Heiko Schocher4dd83492011-11-01 20:00:35 +000051#define CONFIG_BOOTP_DNS
52#define CONFIG_BOOTP_DNS2
53#define CONFIG_BOOTP_SEND_HOSTNAME
54#define CONFIG_NET_RETRY_COUNT 10
Heiko Schocher4dd83492011-11-01 20:00:35 +000055#define CONFIG_CMD_MII
56#define CONFIG_SYS_DCACHE_OFF
57#define CONFIG_RESET_PHY_R
58
59/* I2C */
Vitaly Andrianove8459dc2014-04-04 13:16:52 -040060#define CONFIG_SYS_I2C
61#define CONFIG_SYS_I2C_DAVINCI
62#define CONFIG_SYS_DAVINCI_I2C_SPEED 400000
63#define CONFIG_SYS_DAVINCI_I2C_SLAVE 0x10 /* SMBus host address */
Heiko Schocher4dd83492011-11-01 20:00:35 +000064
65/* NAND: socketed, two chipselects, normally 2 GBytes */
66#define CONFIG_NAND_DAVINCI
67#define CONFIG_SYS_NAND_CS 2
68#define CONFIG_SYS_NAND_USE_FLASH_BBT
69#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
70#define CONFIG_SYS_NAND_PAGE_2K
71
72#define CONFIG_SYS_NAND_LARGEPAGE
73#define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, }
74/* socket has two chipselects, nCE0 gated by address BIT(14) */
75#define CONFIG_SYS_MAX_NAND_DEVICE 1
Heiko Schocher4dd83492011-11-01 20:00:35 +000076
77/* SPI support */
78#define CONFIG_SPI
79#define CONFIG_SPI_FLASH
80#define CONFIG_SPI_FLASH_STMICRO
81#define CONFIG_DAVINCI_SPI
82#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
83#define CONFIG_SYS_SPI_CLK davinci_clk_get(SPI_PLLDIV)
84#define CONFIG_SF_DEFAULT_SPEED 3000000
85#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
86#define CONFIG_CMD_SF
87
88/* SD/MMC */
89#define CONFIG_MMC
90#define CONFIG_GENERIC_MMC
91#define CONFIG_DAVINCI_MMC
92#define CONFIG_MMC_MBLOCK
93
94/* U-Boot command configuration */
95#include <config_cmd_default.h>
96
97#define CONFIG_CMD_BDI
98#undef CONFIG_CMD_FLASH
99#undef CONFIG_CMD_FPGA
100#undef CONFIG_CMD_SETGETDCR
101#define CONFIG_CMD_ASKENV
102#define CONFIG_CMD_CACHE
103#define CONFIG_CMD_DHCP
104#define CONFIG_CMD_I2C
105#define CONFIG_CMD_PING
106#define CONFIG_CMD_SAVES
107
Hadli, Manjunath8f5d4682012-02-06 00:30:44 +0000108#ifdef CONFIG_CMD_BDI
109#define CONFIG_CLOCKS
110#endif
111
Heiko Schocher4dd83492011-11-01 20:00:35 +0000112#ifdef CONFIG_MMC
113#define CONFIG_DOS_PARTITION
114#define CONFIG_CMD_EXT2
115#define CONFIG_CMD_FAT
116#define CONFIG_CMD_MMC
117#endif
118
119#ifdef CONFIG_NAND_DAVINCI
120#define CONFIG_CMD_MTDPARTS
121#define CONFIG_MTD_PARTITIONS
122#define CONFIG_MTD_DEVICE
123#define CONFIG_CMD_NAND
124#define CONFIG_CMD_UBI
Heiko Schocher6be6db52012-01-16 21:20:09 +0000125#define CONFIG_CMD_UBIFS
Heiko Schocher4dd83492011-11-01 20:00:35 +0000126#define CONFIG_RBTREE
Heiko Schocher6be6db52012-01-16 21:20:09 +0000127#define CONFIG_LZO
Heiko Schocher4dd83492011-11-01 20:00:35 +0000128#endif
129
130#define CONFIG_CRC32_VERIFY
131#define CONFIG_MX_CYCLIC
132
133/* U-Boot general configuration */
Heiko Schocher4dd83492011-11-01 20:00:35 +0000134#define CONFIG_BOOTFILE "uImage" /* Boot file name */
135#define CONFIG_SYS_PROMPT "cam_enc_4xx> " /* Monitor Command Prompt */
136#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
137#define CONFIG_SYS_PBSIZE /* Print buffer size */ \
138 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
139#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
140#define CONFIG_SYS_HUSH_PARSER
Heiko Schocher4dd83492011-11-01 20:00:35 +0000141#define CONFIG_SYS_LONGHELP
142
Heiko Schocher6be6db52012-01-16 21:20:09 +0000143#define CONFIG_MENU
144#define CONFIG_MENU_SHOW
145#define CONFIG_FIT
Heiko Schocher6be6db52012-01-16 21:20:09 +0000146#define CONFIG_BOARD_IMG_ADDR_R 0x80000000
147
Heiko Schocher4dd83492011-11-01 20:00:35 +0000148#ifdef CONFIG_NAND_DAVINCI
Heiko Schocher6be6db52012-01-16 21:20:09 +0000149#define CONFIG_ENV_SIZE (16 << 10)
Heiko Schocher4dd83492011-11-01 20:00:35 +0000150#define CONFIG_ENV_IS_IN_NAND
Heiko Schocher6be6db52012-01-16 21:20:09 +0000151#define CONFIG_ENV_OFFSET 0x180000
Heiko Schocher24efef92012-03-07 04:10:00 +0000152#define CONFIG_ENV_RANGE 0x040000
Heiko Schocher6be6db52012-01-16 21:20:09 +0000153#define CONFIG_ENV_OFFSET_REDUND 0x1c0000
Heiko Schocher4dd83492011-11-01 20:00:35 +0000154#undef CONFIG_ENV_IS_IN_FLASH
155#endif
156
157#if defined(CONFIG_MMC) && !defined(CONFIG_ENV_IS_IN_NAND)
158#define CONFIG_CMD_ENV
Heiko Schocher6be6db52012-01-16 21:20:09 +0000159#define CONFIG_SYS_MMC_ENV_DEV 0
Heiko Schocher4dd83492011-11-01 20:00:35 +0000160#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
161#define CONFIG_ENV_OFFSET (51 << 9) /* Sector 51 */
162#define CONFIG_ENV_IS_IN_MMC
163#undef CONFIG_ENV_IS_IN_FLASH
164#endif
165
166#define CONFIG_BOOTDELAY 3
Heiko Schocher6be6db52012-01-16 21:20:09 +0000167/*
168 * 24MHz InputClock / 15 prediv -> 1.6 MHz timer running
169 * Timeout 1 second.
170 */
171#define CONFIG_AIT_TIMER_TIMEOUT 0x186a00
Heiko Schocher4dd83492011-11-01 20:00:35 +0000172
173#define CONFIG_CMDLINE_EDITING
174#define CONFIG_VERSION_VARIABLE
175#define CONFIG_TIMESTAMP
176
177/* U-Boot memory configuration */
Heiko Schocher4dd83492011-11-01 20:00:35 +0000178#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */
179#define CONFIG_SYS_MEMTEST_START 0x80000000 /* physical address */
180#define CONFIG_SYS_MEMTEST_END 0x81000000 /* test 16MB RAM */
181
182/* Linux interfacing */
183#define CONFIG_CMDLINE_TAG
184#define CONFIG_SETUP_MEMORY_TAGS
185#define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */
186#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */
187
188#define MTDIDS_DEFAULT "nand0=davinci_nand.0"
Heiko Schocher6be6db52012-01-16 21:20:09 +0000189#define MTDPARTS_DEFAULT \
190 "mtdparts=" \
191 "davinci_nand.0:" \
192 "128k(spl)," \
193 "384k(UBLheader)," \
194 "1m(u-boot)," \
195 "512k(env)," \
196 "-(ubi)"
Heiko Schocher4dd83492011-11-01 20:00:35 +0000197
Heiko Schocher6be6db52012-01-16 21:20:09 +0000198#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
199#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
Heiko Schocher4dd83492011-11-01 20:00:35 +0000200
201/* Defines for SPL */
Tom Rini3f7f2412012-08-14 12:27:13 -0700202#define CONFIG_SPL_FRAMEWORK
203#define CONFIG_SPL_BOARD_INIT
Heiko Schocher24efef92012-03-07 04:10:00 +0000204#define CONFIG_SPL_LIBGENERIC_SUPPORT
Heiko Schocher4dd83492011-11-01 20:00:35 +0000205#define CONFIG_SPL_NAND_SUPPORT
Scott Wood6f2f01b2012-09-20 19:09:07 -0500206#define CONFIG_SPL_NAND_BASE
207#define CONFIG_SPL_NAND_DRIVERS
208#define CONFIG_SPL_NAND_ECC
Heiko Schocher4dd83492011-11-01 20:00:35 +0000209#define CONFIG_SPL_NAND_SIMPLE
Heiko Schocher4dd83492011-11-01 20:00:35 +0000210#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
211#define CONFIG_SPL_SERIAL_SUPPORT
212#define CONFIG_SPL_POST_MEM_SUPPORT
213#define CONFIG_SPL_LDSCRIPT "$(BOARDDIR)/u-boot-spl.lds"
214#define CONFIG_SPL_STACK (0x00010000 + 0x7f00)
215
Heiko Schocher24efef92012-03-07 04:10:00 +0000216#define CONFIG_SPL_TEXT_BASE 0x00000020 /*CONFIG_SYS_SRAM_START*/
Masahiro Yamada1affd4d2013-09-01 15:04:27 +0900217/* Provide at least 16MB spacing between us and the Linux Kernel image */
218#define CONFIG_SPL_PAD_TO 12320
Albert ARIBAUDe7497892013-04-12 05:14:31 +0000219#define CONFIG_SPL_MAX_FOOTPRINT 12288
Heiko Schocher4dd83492011-11-01 20:00:35 +0000220
221#ifndef CONFIG_SPL_BUILD
222#define CONFIG_SYS_TEXT_BASE 0x81080000
223#endif
224
225#define CONFIG_SYS_NAND_BASE 0x02000000
226#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
227 CONFIG_SYS_NAND_PAGE_SIZE)
228
229#define CONFIG_SYS_NAND_ECCPOS { \
230 24, 25, 26, 27, 28, \
231 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \
232 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
233 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
234 59, 60, 61, 62, 63 }
235#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
236#define CONFIG_SYS_NAND_ECCSIZE 0x200
237#define CONFIG_SYS_NAND_ECCBYTES 10
Tom Rinid8794da2013-12-18 14:43:08 -0500238#define CONFIG_SYS_NAND_MAX_OOBFREE 2
239#define CONFIG_SYS_NAND_MAX_ECCPOS 56
Heiko Schocher4dd83492011-11-01 20:00:35 +0000240#define CONFIG_SYS_NAND_OOBSIZE 64
241#define CONFIG_SYS_NAND_5_ADDR_CYCLE
Heiko Schocher4dd83492011-11-01 20:00:35 +0000242
243/*
244 * RBL searches from Block n (n = 1..24)
245 * so we can define, how many UBL Headers
246 * we can write before the real spl code
247 */
Heiko Schocher4dd83492011-11-01 20:00:35 +0000248#define CONFIG_SYS_NROF_PAGES_NAND_SPL 6
249
250#define CONFIG_SYS_NAND_U_BOOT_DST 0x81080000 /* u-boot TEXT_BASE */
251#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
252
253/*
254 * Post tests for memory testing
255 */
256#define CONFIG_POST CONFIG_SYS_POST_MEMORY
257#define _POST_WORD_ADDR 0x0
258
Heiko Schocher4dd83492011-11-01 20:00:35 +0000259#define CONFIG_DISPLAY_BOARDINFO
260
261#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
262
Heiko Schocher6be6db52012-01-16 21:20:09 +0000263#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
264#define CONFIG_SYS_NAND_U_BOOT_SIZE 0xa0000
Heiko Schocher24efef92012-03-07 04:10:00 +0000265#define CONFIG_SYS_NAND_U_BOOT_ERA_SIZE 0x100000
Heiko Schocher4dd83492011-11-01 20:00:35 +0000266
Heiko Schocher4dd83492011-11-01 20:00:35 +0000267/* for UBL header */
268#define CONFIG_SYS_UBL_BLOCK (CONFIG_SYS_NAND_PAGE_SIZE)
269
270#define CONFIG_SYS_DM36x_PLL1_PLLM 0x55
271#define CONFIG_SYS_DM36x_PLL1_PREDIV 0x8005
272#define CONFIG_SYS_DM36x_PLL2_PLLM 0x09
273#define CONFIG_SYS_DM36x_PLL2_PREDIV 0x8000
274#define CONFIG_SYS_DM36x_PERI_CLK_CTRL 0x243F04FC
275#define CONFIG_SYS_DM36x_PLL1_PLLDIV1 0x801b
276#define CONFIG_SYS_DM36x_PLL1_PLLDIV2 0x8001
277/* POST DIV 680/2 = 340Mhz -> MJCP and HDVICP bus interface clock */
278#define CONFIG_SYS_DM36x_PLL1_PLLDIV3 0x8001
279/*
280 * POST DIV 680/4 = 170Mhz -> EDMA/Peripheral CFG0(1/2 MJCP/HDVICP bus
281 * interface clk)
282 */
283#define CONFIG_SYS_DM36x_PLL1_PLLDIV4 0x8003
284/* POST DIV 680/2 = 340Mhz -> VPSS */
285#define CONFIG_SYS_DM36x_PLL1_PLLDIV5 0x8001
286/* POST DIV 680/9 = 75.6 Mhz -> VENC */
287#define CONFIG_SYS_DM36x_PLL1_PLLDIV6 0x8008
288/*
289 * POST DIV 680/1 = 680Mhz -> DDRx2(with internal divider of 2, clock boils
290 * down to 340 Mhz)
291 */
292#define CONFIG_SYS_DM36x_PLL1_PLLDIV7 0x8000
293/* POST DIV 680/7= 97Mhz-> MMC0/SD0 */
294#define CONFIG_SYS_DM36x_PLL1_PLLDIV8 0x8006
295/* POST DIV 680/28 = 24.3Mhz-> CLKOUT */
296#define CONFIG_SYS_DM36x_PLL1_PLLDIV9 0x801b
297
298#define CONFIG_SYS_DM36x_PLL2_PLLDIV1 0x8011
299/* POST DIV 432/1=432 Mhz -> ARM926/(HDVICP block) clk */
300#define CONFIG_SYS_DM36x_PLL2_PLLDIV2 0x8000
301#define CONFIG_SYS_DM36x_PLL2_PLLDIV3 0x8001
302/* POST DIV 432/21= 20.5714 Mhz->VOICE Codec clk */
303#define CONFIG_SYS_DM36x_PLL2_PLLDIV4 0x8014
304/* POST DIV 432/16=27 Mhz -> VENC(For SD modes, requires) */
305#define CONFIG_SYS_DM36x_PLL2_PLLDIV5 0x800f
306
307/*
308 * READ LATENCY 7 (CL + 2)
309 * CONFIG_PWRDNEN = 1
310 * CONFIG_EXT_STRBEN = 1
311 */
312#define CONFIG_SYS_DM36x_DDR2_DDRPHYCR (0 \
313 | DV_DDR_PHY_EXT_STRBEN \
314 | DV_DDR_PHY_PWRDNEN \
315 | (7 << DV_DDR_PHY_RD_LATENCY_SHIFT))
316
317/*
318 * T_RFC = (trfc/DDR_CLK) - 1 = (195 / 2.941) - 1
319 * T_RP = (trp/DDR_CLK) - 1 = (12.5 / 2.941) - 1
320 * T_RCD = (trcd/DDR_CLK) - 1 = (12.5 / 2.941) - 1
321 * T_WR = (twr/DDR_CLK) - 1 = (15 / 2.941) - 1
322 * T_RAS = (tras/DDR_CLK) - 1 = (45 / 2.941) - 1
323 * T_RC = (trc/DDR_CLK) - 1 = (57.5 / 2.941) - 1
324 * T_RRD = (trrd/DDR_CLK) - 1 = (7.5 / 2.941) - 1
325 * T_WTR = (twtr/DDR_CLK) - 1 = (7.5 / 2.941) - 1
326 */
327#define CONFIG_SYS_DM36x_DDR2_SDTIMR (0 \
328 | (66 << DV_DDR_SDTMR1_RFC_SHIFT) \
329 | (4 << DV_DDR_SDTMR1_RP_SHIFT) \
330 | (4 << DV_DDR_SDTMR1_RCD_SHIFT) \
331 | (5 << DV_DDR_SDTMR1_WR_SHIFT) \
332 | (14 << DV_DDR_SDTMR1_RAS_SHIFT) \
333 | (19 << DV_DDR_SDTMR1_RC_SHIFT) \
334 | (2 << DV_DDR_SDTMR1_RRD_SHIFT) \
335 | (2 << DV_DDR_SDTMR1_WTR_SHIFT))
336
337/*
338 * T_RASMAX = (trasmax/refresh_rate) - 1 = (70K / 7812.6) - 1
339 * T_XP = tCKE - 1 = 3 - 2
340 * T_XSNR= ((trfc + 10)/DDR_CLK) - 1 = (205 / 2.941) - 1
341 * T_XSRD = txsrd - 1 = 200 - 1
342 * T_RTP = (trtp/DDR_CLK) - 1 = (7.5 / 2.941) - 1
343 * T_CKE = tcke - 1 = 3 - 1
344 */
345#define CONFIG_SYS_DM36x_DDR2_SDTIMR2 (0 \
346 | (8 << DV_DDR_SDTMR2_RASMAX_SHIFT) \
347 | (2 << DV_DDR_SDTMR2_XP_SHIFT) \
348 | (69 << DV_DDR_SDTMR2_XSNR_SHIFT) \
349 | (199 << DV_DDR_SDTMR2_XSRD_SHIFT) \
350 | (2 << DV_DDR_SDTMR2_RTP_SHIFT) \
351 | (2 << DV_DDR_SDTMR2_CKE_SHIFT))
352
353/* PR_OLD_COUNT = 0xfe */
354#define CONFIG_SYS_DM36x_DDR2_PBBPR 0x000000FE
355/* refresh rate = 0x768 */
356#define CONFIG_SYS_DM36x_DDR2_SDRCR 0x00000768
357
358#define CONFIG_SYS_DM36x_DDR2_SDBCR (0 \
359 | (2 << DV_DDR_SDCR_PAGESIZE_SHIFT) \
360 | (3 << DV_DDR_SDCR_IBANK_SHIFT) \
361 | (5 << DV_DDR_SDCR_CL_SHIFT) \
362 | (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) \
363 | (1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) \
364 | (1 << DV_DDR_SDCR_DDREN_SHIFT) \
365 | (0 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) \
366 | (1 << DV_DDR_SDCR_DDR2EN_SHIFT) \
367 | (1 << DV_DDR_SDCR_DDR_DDQS_SHIFT) \
368 | (1 << DV_DDR_SDCR_BOOTUNLOCK_SHIFT))
369
370#define CONFIG_SYS_DM36x_AWCCR 0xff
371#define CONFIG_SYS_DM36x_AB1CR 0x40400204
372#define CONFIG_SYS_DM36x_AB2CR 0x04ca2650
373
374/* All Video Inputs */
375#define CONFIG_SYS_DM36x_PINMUX0 0x00000000
376/*
377 * All Video Outputs,
378 * GPIO 86, 87 + 90 0x0000f030
379 */
380#define CONFIG_SYS_DM36x_PINMUX1 0x00530002
381#define CONFIG_SYS_DM36x_PINMUX2 0x00001815
382/*
383 * SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs
384 * GPIO 25 0x60000000
385 */
386#define CONFIG_SYS_DM36x_PINMUX3 0x9b5affff
387/*
388 * MMC/SD0 instead of MS, SPI0
389 * GPIO 34 0x0000c000
390 */
391#define CONFIG_SYS_DM36x_PINMUX4 0x00002655
392
393/*
394 * Default environment settings
395 */
Heiko Schocher4dd83492011-11-01 20:00:35 +0000396
397#define DVN4XX_UBOOT_ADDR_R_RAM 0x80000000
398/* (DVN4XX_UBOOT_ADDR_R_RAM + CONFIG_SYS_NAND_PAGE_SIZE) */
399#define DVN4XX_UBOOT_ADDR_R_NAND_SPL 0x80000800
400/*
401 * (DVN4XX_UBOOT_ADDR_R_NAND_SPL + (CONFIG_SYS_NROF_PAGES_NAND_SPL * \
402 * CONFIG_SYS_NAND_PAGE_SIZE))
403 */
404#define DVN4XX_UBOOT_ADDR_R_UBOOT 0x80003800
405
406#define CONFIG_EXTRA_ENV_SETTINGS \
Marek Vasut93ea89f2012-09-23 17:41:23 +0200407 "u_boot_addr_r=" __stringify(DVN4XX_UBOOT_ADDR_R_RAM) "\0" \
408 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.ubl\0" \
Heiko Schocher6be6db52012-01-16 21:20:09 +0000409 "load=tftp ${u_boot_addr_r} ${u-boot}\0" \
Marek Vasut93ea89f2012-09-23 17:41:23 +0200410 "pagesz=" __stringify(CONFIG_SYS_NAND_PAGE_SIZE) "\0" \
Heiko Schocher6be6db52012-01-16 21:20:09 +0000411 "writeheader=nandrbl rbl;nand erase 20000 ${pagesz};" \
412 "nand write ${u_boot_addr_r} 20000 ${pagesz};" \
Heiko Schocher4dd83492011-11-01 20:00:35 +0000413 "nandrbl uboot\0" \
Heiko Schocher6be6db52012-01-16 21:20:09 +0000414 "writenand_spl=nandrbl rbl;nand erase 0 3000;" \
Marek Vasut93ea89f2012-09-23 17:41:23 +0200415 "nand write " __stringify(DVN4XX_UBOOT_ADDR_R_NAND_SPL) \
Heiko Schocher6be6db52012-01-16 21:20:09 +0000416 " 0 3000;nandrbl uboot\0" \
Heiko Schocher4dd83492011-11-01 20:00:35 +0000417 "writeuboot=nandrbl uboot;" \
Marek Vasut93ea89f2012-09-23 17:41:23 +0200418 "nand erase " __stringify(CONFIG_SYS_NAND_U_BOOT_OFFS) " "\
419 __stringify(CONFIG_SYS_NAND_U_BOOT_ERA_SIZE) \
420 ";nand write " __stringify(DVN4XX_UBOOT_ADDR_R_UBOOT) \
421 " " __stringify(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
422 __stringify(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0" \
Heiko Schocher4dd83492011-11-01 20:00:35 +0000423 "update=run load writenand_spl writeuboot\0" \
Heiko Schocher6be6db52012-01-16 21:20:09 +0000424 "bootcmd=run net_nfs\0" \
Heiko Schocher4dd83492011-11-01 20:00:35 +0000425 "rootpath=/opt/eldk-arm/arm\0" \
Heiko Schocher6be6db52012-01-16 21:20:09 +0000426 "mtdids=" MTDIDS_DEFAULT "\0" \
427 "mtdparts=" MTDPARTS_DEFAULT "\0" \
428 "netdev=eth0\0" \
429 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
430 "addmisc=setenv bootargs ${bootargs} app_reset=${app_reset}\0" \
431 "addcon=setenv bootargs ${bootargs} console=ttyS0," \
432 "${baudrate}n8\0" \
433 "addip=setenv bootargs ${bootargs} " \
434 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
435 ":${hostname}:${netdev}:off eth=${ethaddr} panic=1\0" \
436 "rootpath=/opt/eldk-arm/arm\0" \
437 "nfsargs=setenv bootargs root=/dev/nfs rw " \
438 "nfsroot=${serverip}:${rootpath}\0" \
Marek Vasut93ea89f2012-09-23 17:41:23 +0200439 "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage \0" \
Heiko Schocher6be6db52012-01-16 21:20:09 +0000440 "kernel_addr_r=80600000\0" \
441 "load_kernel=tftp ${kernel_addr_r} ${bootfile}\0" \
Joe Hershberger949a7712012-11-01 16:54:18 +0000442 "ubi_load_kernel=ubi part ubi 2048;ubifsmount ubi:${img_volume};" \
Heiko Schocher6be6db52012-01-16 21:20:09 +0000443 "ubifsload ${kernel_addr_r} boot/uImage\0" \
Marek Vasut93ea89f2012-09-23 17:41:23 +0200444 "fit_addr_r=" __stringify(CONFIG_BOARD_IMG_ADDR_R) "\0" \
445 "img_addr_r=" __stringify(CONFIG_BOARD_IMG_ADDR_R) "\0" \
446 "img_file=" __stringify(CONFIG_HOSTNAME) "/ait.itb\0" \
Heiko Schocher6be6db52012-01-16 21:20:09 +0000447 "header_addr=20000\0" \
448 "img_writeheader=nandrbl rbl;" \
449 "nand erase ${header_addr} ${pagesz};" \
450 "nand write ${img_addr_r} ${header_addr} ${pagesz};" \
451 "nandrbl uboot\0" \
452 "img_writespl=nandrbl rbl;nand erase 0 3000;" \
453 "nand write ${img_addr_r} 0 3000;nandrbl uboot\0" \
454 "img_writeuboot=nandrbl uboot;" \
Marek Vasut93ea89f2012-09-23 17:41:23 +0200455 "nand erase " __stringify(CONFIG_SYS_NAND_U_BOOT_OFFS) " "\
456 __stringify(CONFIG_SYS_NAND_U_BOOT_ERA_SIZE) \
Heiko Schocher6be6db52012-01-16 21:20:09 +0000457 ";nand write ${img_addr_r} " \
Marek Vasut93ea89f2012-09-23 17:41:23 +0200458 __stringify(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
459 __stringify(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0" \
Heiko Schocher6be6db52012-01-16 21:20:09 +0000460 "img_writedfenv=ubi part ubi 2048;" \
461 "ubi write ${img_addr_r} default ${filesize}\0" \
462 "img_volume=rootfs1\0" \
Heiko Schocher24efef92012-03-07 04:10:00 +0000463 "img_writeramdisk=ubi part ubi 2048;" \
Heiko Schocher6be6db52012-01-16 21:20:09 +0000464 "ubi write ${img_addr_r} ${img_volume} ${filesize}\0" \
465 "load_img=tftp ${fit_addr_r} ${img_file}\0" \
466 "net_nfs=run load_kernel; " \
467 "run nfsargs addip addcon addmtd addmisc;" \
468 "bootm ${kernel_addr_r}\0" \
469 "ubi_ubi=run ubi_load_kernel; " \
470 "run ubiargs addip addcon addmtd addmisc;" \
471 "bootm ${kernel_addr_r}\0" \
472 "ubiargs=setenv bootargs ubi.mtd=4,2048" \
473 " root=ubi0:${img_volume} rw rootfstype=ubifs\0" \
474 "app_reset=no\0" \
475 "dvn_app_vers=void\0" \
476 "dvn_boot_vers=void\0" \
477 "savenewvers=run savetmpparms restoreparms; saveenv;" \
478 "run restoretmpparms\0" \
479 "savetmpparms=setenv y_ipaddr ${ipaddr};" \
480 "setenv y_netmask ${netmask};" \
481 "setenv y_serverip ${serverip};" \
482 "setenv y_gatewayip ${gatewayip}\0" \
483 "saveparms=setenv x_ipaddr ${ipaddr};" \
484 "setenv x_netmask ${netmask};" \
485 "setenv x_serverip ${serverip};" \
486 "setenv x_gatewayip ${gatewayip}\0" \
487 "restoreparms=setenv ipaddr ${x_ipaddr};" \
488 "setenv netmask ${x_netmask};" \
489 "setenv serverip ${x_serverip};" \
490 "setenv gatewayip ${x_gatewayip}\0" \
491 "restoretmpparms=setenv ipaddr ${y_ipaddr};" \
492 "setenv netmask ${y_netmask};" \
493 "setenv serverip ${y_serverip};" \
494 "setenv gatewayip ${y_gatewayip}\0" \
Heiko Schocher4dd83492011-11-01 20:00:35 +0000495 "\0"
496
497/* USB Configuration */
498#define CONFIG_USB_DAVINCI
499#define CONFIG_MUSB_HCD
500#define CONFIG_DV_USBPHY_CTL (USBPHY_SESNDEN | USBPHY_VBDTCTEN | \
501 USBPHY_PHY24MHZ)
502
503#define CONFIG_CMD_USB /* include support for usb cmd */
504#define CONFIG_USB_STORAGE /* MSC class support */
505#define CONFIG_CMD_STORAGE /* inclue support for usb-storage cmd */
506#define CONFIG_CMD_FAT /* inclue support for FAT/storage */
507#define CONFIG_DOS_PARTITION /* inclue support for FAT/storage */
508
509#undef DAVINCI_DM365EVM
510#define PINMUX4_USBDRVBUS_BITCLEAR 0x3000
511#define PINMUX4_USBDRVBUS_BITSET 0x2000
512
513#endif /* __CONFIG_H */