blob: dcf2194e9a7c329570d3990dbeb580a7ae4d316c [file] [log] [blame]
Tom Rini624d2ca2018-05-20 09:47:45 -04001// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
Patrice Chotard3b291212018-04-27 11:01:55 +02002/*
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
4 */
5
Patrick Delaunay0d5fbad2020-11-06 19:01:51 +01006#define LOG_CATEGORY UCLASS_PHY
7
Patrice Chotard3b291212018-04-27 11:01:55 +02008#include <common.h>
9#include <clk.h>
Patrick Delaunay9406f972022-04-26 14:37:48 +020010#include <clk-uclass.h>
Patrice Chotard3b291212018-04-27 11:01:55 +020011#include <div64.h>
12#include <dm.h>
13#include <fdtdec.h>
14#include <generic-phy.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060015#include <log.h>
Patrice Chotard3b291212018-04-27 11:01:55 +020016#include <reset.h>
17#include <syscon.h>
18#include <usb.h>
19#include <asm/io.h>
Simon Glass336d4612020-02-03 07:36:16 -070020#include <dm/device_compat.h>
Patrick Delaunay9406f972022-04-26 14:37:48 +020021#include <dm/lists.h>
Patrice Chotardda6473c2022-04-22 09:39:00 +020022#include <dm/of_access.h>
23#include <linux/bitfield.h>
Patrice Chotard3b291212018-04-27 11:01:55 +020024#include <linux/bitops.h>
Simon Glassc05ed002020-05-10 11:40:11 -060025#include <linux/delay.h>
Patrice Chotard3b291212018-04-27 11:01:55 +020026#include <power/regulator.h>
27
28/* USBPHYC registers */
29#define STM32_USBPHYC_PLL 0x0
30#define STM32_USBPHYC_MISC 0x8
Patrice Chotardda6473c2022-04-22 09:39:00 +020031#define STM32_USBPHYC_TUNE(X) (0x10C + ((X) * 0x100))
Patrice Chotard3b291212018-04-27 11:01:55 +020032
33/* STM32_USBPHYC_PLL bit fields */
34#define PLLNDIV GENMASK(6, 0)
35#define PLLNDIV_SHIFT 0
36#define PLLFRACIN GENMASK(25, 10)
37#define PLLFRACIN_SHIFT 10
38#define PLLEN BIT(26)
39#define PLLSTRB BIT(27)
40#define PLLSTRBYP BIT(28)
41#define PLLFRACCTL BIT(29)
42#define PLLDITHEN0 BIT(30)
43#define PLLDITHEN1 BIT(31)
44
45/* STM32_USBPHYC_MISC bit fields */
46#define SWITHOST BIT(0)
47
Patrice Chotardda6473c2022-04-22 09:39:00 +020048/* STM32_USBPHYC_TUNE bit fields */
49#define INCURREN BIT(0)
50#define INCURRINT BIT(1)
51#define LFSCAPEN BIT(2)
52#define HSDRVSLEW BIT(3)
53#define HSDRVDCCUR BIT(4)
54#define HSDRVDCLEV BIT(5)
55#define HSDRVCURINCR BIT(6)
56#define FSDRVRFADJ BIT(7)
57#define HSDRVRFRED BIT(8)
58#define HSDRVCHKITRM GENMASK(12, 9)
59#define HSDRVCHKZTRM GENMASK(14, 13)
60#define OTPCOMP GENMASK(19, 15)
61#define SQLCHCTL GENMASK(21, 20)
62#define HDRXGNEQEN BIT(22)
63#define HSRXOFF GENMASK(24, 23)
64#define HSFALLPREEM BIT(25)
65#define SHTCCTCTLPROT BIT(26)
66#define STAGSEL BIT(27)
67
Patrice Chotard3b291212018-04-27 11:01:55 +020068#define MAX_PHYS 2
69
Patrick Delaunay901f6952019-03-29 15:42:13 +010070/* max 100 us for PLL lock and 100 us for PHY init */
71#define PLL_INIT_TIME_US 200
Patrice Chotard3b291212018-04-27 11:01:55 +020072#define PLL_PWR_DOWN_TIME_US 5
73#define PLL_FVCO 2880 /* in MHz */
74#define PLL_INFF_MIN_RATE 19200000 /* in Hz */
75#define PLL_INFF_MAX_RATE 38400000 /* in Hz */
76
Patrick Delaunay9406f972022-04-26 14:37:48 +020077/* USBPHYC_CLK48 */
78#define USBPHYC_CLK48_FREQ 48000000 /* in Hz */
79
Patrice Chotardda6473c2022-04-22 09:39:00 +020080enum boosting_vals {
81 BOOST_1000_UA = 1000,
82 BOOST_2000_UA = 2000,
83};
84
85enum dc_level_vals {
86 DC_MINUS_5_TO_7_MV,
87 DC_PLUS_5_TO_7_MV,
88 DC_PLUS_10_TO_14_MV,
89 DC_MAX,
90};
91
92enum current_trim {
93 CUR_NOMINAL,
94 CUR_PLUS_1_56_PCT,
95 CUR_PLUS_3_12_PCT,
96 CUR_PLUS_4_68_PCT,
97 CUR_PLUS_6_24_PCT,
98 CUR_PLUS_7_8_PCT,
99 CUR_PLUS_9_36_PCT,
100 CUR_PLUS_10_92_PCT,
101 CUR_PLUS_12_48_PCT,
102 CUR_PLUS_14_04_PCT,
103 CUR_PLUS_15_6_PCT,
104 CUR_PLUS_17_16_PCT,
105 CUR_PLUS_19_01_PCT,
106 CUR_PLUS_20_58_PCT,
107 CUR_PLUS_22_16_PCT,
108 CUR_PLUS_23_73_PCT,
109 CUR_MAX,
110};
111
112enum impedance_trim {
113 IMP_NOMINAL,
114 IMP_MINUS_2_OHMS,
115 IMP_MINUS_4_OMHS,
116 IMP_MINUS_6_OHMS,
117 IMP_MAX,
118};
119
120enum squelch_level {
121 SQLCH_NOMINAL,
122 SQLCH_PLUS_7_MV,
123 SQLCH_MINUS_5_MV,
124 SQLCH_PLUS_14_MV,
125 SQLCH_MAX,
126};
127
128enum rx_offset {
129 NO_RX_OFFSET,
130 RX_OFFSET_PLUS_5_MV,
131 RX_OFFSET_PLUS_10_MV,
132 RX_OFFSET_MINUS_5_MV,
133 RX_OFFSET_MAX,
134};
135
Patrice Chotard3b291212018-04-27 11:01:55 +0200136struct pll_params {
137 u8 ndiv;
138 u16 frac;
139};
140
141struct stm32_usbphyc {
142 fdt_addr_t base;
143 struct clk clk;
Patrick Delaunayc50151d2019-03-29 15:42:11 +0100144 struct udevice *vdda1v1;
145 struct udevice *vdda1v8;
Patrice Chotard3b291212018-04-27 11:01:55 +0200146 struct stm32_usbphyc_phy {
147 struct udevice *vdd;
Patrick Delaunayc4801382020-10-15 14:50:57 +0200148 struct udevice *vbus;
Patrice Chotard3b291212018-04-27 11:01:55 +0200149 bool init;
150 bool powered;
151 } phys[MAX_PHYS];
Patrick Delaunay3c2db622022-04-26 14:37:47 +0200152 int n_pll_cons;
Patrice Chotard3b291212018-04-27 11:01:55 +0200153};
154
Patrick Delaunaye1904ab2019-03-29 15:42:12 +0100155static void stm32_usbphyc_get_pll_params(u32 clk_rate,
156 struct pll_params *pll_params)
Patrice Chotard3b291212018-04-27 11:01:55 +0200157{
158 unsigned long long fvco, ndiv, frac;
159
160 /*
161 * | FVCO = INFF*2*(NDIV + FRACT/2^16 ) when DITHER_DISABLE[1] = 1
162 * | FVCO = 2880MHz
163 * | NDIV = integer part of input bits to set the LDF
164 * | FRACT = fractional part of input bits to set the LDF
165 * => PLLNDIV = integer part of (FVCO / (INFF*2))
166 * => PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
167 * <=> PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
168 */
169 fvco = (unsigned long long)PLL_FVCO * 1000000; /* In Hz */
170
171 ndiv = fvco;
172 do_div(ndiv, (clk_rate * 2));
173 pll_params->ndiv = (u8)ndiv;
174
175 frac = fvco * (1 << 16);
176 do_div(frac, (clk_rate * 2));
177 frac = frac - (ndiv * (1 << 16));
178 pll_params->frac = (u16)frac;
179}
180
181static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
182{
183 struct pll_params pll_params;
184 u32 clk_rate = clk_get_rate(&usbphyc->clk);
185 u32 usbphyc_pll;
186
187 if ((clk_rate < PLL_INFF_MIN_RATE) || (clk_rate > PLL_INFF_MAX_RATE)) {
Patrick Delaunay0d5fbad2020-11-06 19:01:51 +0100188 log_debug("input clk freq (%dHz) out of range\n",
189 clk_rate);
Patrice Chotard3b291212018-04-27 11:01:55 +0200190 return -EINVAL;
191 }
192
193 stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
194
195 usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP;
196 usbphyc_pll |= ((pll_params.ndiv << PLLNDIV_SHIFT) & PLLNDIV);
197
198 if (pll_params.frac) {
199 usbphyc_pll |= PLLFRACCTL;
200 usbphyc_pll |= ((pll_params.frac << PLLFRACIN_SHIFT)
201 & PLLFRACIN);
202 }
203
204 writel(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
205
Patrick Delaunay0d5fbad2020-11-06 19:01:51 +0100206 log_debug("input clk freq=%dHz, ndiv=%d, frac=%d\n",
207 clk_rate, pll_params.ndiv, pll_params.frac);
Patrice Chotard3b291212018-04-27 11:01:55 +0200208
209 return 0;
210}
211
Patrice Chotard3b291212018-04-27 11:01:55 +0200212static bool stm32_usbphyc_is_powered(struct stm32_usbphyc *usbphyc)
213{
214 int i;
215
216 for (i = 0; i < MAX_PHYS; i++) {
217 if (usbphyc->phys[i].powered)
218 return true;
219 }
220
221 return false;
222}
223
Patrick Delaunay3c2db622022-04-26 14:37:47 +0200224static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc)
Patrice Chotard3b291212018-04-27 11:01:55 +0200225{
Patrice Chotard3b291212018-04-27 11:01:55 +0200226 bool pllen = readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN ?
227 true : false;
228 int ret;
229
Patrick Delaunay3c2db622022-04-26 14:37:47 +0200230 /* Check if one consumer has already configured the pll */
231 if (pllen && usbphyc->n_pll_cons) {
232 usbphyc->n_pll_cons++;
233 return 0;
234 }
Patrice Chotard3b291212018-04-27 11:01:55 +0200235
Patrick Delaunaye1904ab2019-03-29 15:42:12 +0100236 if (usbphyc->vdda1v1) {
237 ret = regulator_set_enable(usbphyc->vdda1v1, true);
238 if (ret)
239 return ret;
240 }
241
242 if (usbphyc->vdda1v8) {
243 ret = regulator_set_enable(usbphyc->vdda1v8, true);
244 if (ret)
245 return ret;
246 }
247
Patrice Chotard3b291212018-04-27 11:01:55 +0200248 if (pllen) {
249 clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
250 udelay(PLL_PWR_DOWN_TIME_US);
251 }
252
253 ret = stm32_usbphyc_pll_init(usbphyc);
254 if (ret)
255 return ret;
256
257 setbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
258
Patrick Delaunay901f6952019-03-29 15:42:13 +0100259 /* We must wait PLL_INIT_TIME_US before using PHY */
260 udelay(PLL_INIT_TIME_US);
Patrice Chotard3b291212018-04-27 11:01:55 +0200261
262 if (!(readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN))
263 return -EIO;
264
Patrick Delaunay3c2db622022-04-26 14:37:47 +0200265 usbphyc->n_pll_cons++;
Patrice Chotard3b291212018-04-27 11:01:55 +0200266
267 return 0;
268}
269
Patrick Delaunay3c2db622022-04-26 14:37:47 +0200270static int stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
Patrice Chotard3b291212018-04-27 11:01:55 +0200271{
Patrick Delaunaye1904ab2019-03-29 15:42:12 +0100272 int ret;
Patrice Chotard3b291212018-04-27 11:01:55 +0200273
Patrick Delaunay3c2db622022-04-26 14:37:47 +0200274 usbphyc->n_pll_cons--;
Patrice Chotard3b291212018-04-27 11:01:55 +0200275
Patrick Delaunay3c2db622022-04-26 14:37:47 +0200276 /* Check if other consumer requires pllen */
277 if (usbphyc->n_pll_cons)
Patrice Chotard3b291212018-04-27 11:01:55 +0200278 return 0;
279
280 clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
281
282 /*
283 * We must wait PLL_PWR_DOWN_TIME_US before checking that PLLEN
284 * bit is still clear
285 */
286 udelay(PLL_PWR_DOWN_TIME_US);
287
288 if (readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN)
289 return -EIO;
290
Patrick Delaunaye1904ab2019-03-29 15:42:12 +0100291 if (usbphyc->vdda1v1) {
292 ret = regulator_set_enable(usbphyc->vdda1v1, false);
293 if (ret)
294 return ret;
295 }
296
297 if (usbphyc->vdda1v8) {
298 ret = regulator_set_enable(usbphyc->vdda1v8, false);
299 if (ret)
300 return ret;
301 }
302
Patrice Chotard3b291212018-04-27 11:01:55 +0200303 return 0;
304}
305
Patrick Delaunay3c2db622022-04-26 14:37:47 +0200306static int stm32_usbphyc_phy_init(struct phy *phy)
307{
308 struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
309 struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
310 int ret;
311
312 dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
313 if (usbphyc_phy->init)
314 return 0;
315
316 ret = stm32_usbphyc_pll_enable(usbphyc);
317 if (ret)
318 return log_ret(ret);
319
320 usbphyc_phy->init = true;
321
322 return 0;
323}
324
325static int stm32_usbphyc_phy_exit(struct phy *phy)
326{
327 struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
328 struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
329 int ret;
330
331 dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
332 if (!usbphyc_phy->init)
333 return 0;
334
335 ret = stm32_usbphyc_pll_disable(usbphyc);
336
337 usbphyc_phy->init = false;
338
339 return log_ret(ret);
340}
341
Patrice Chotard3b291212018-04-27 11:01:55 +0200342static int stm32_usbphyc_phy_power_on(struct phy *phy)
343{
344 struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
345 struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
346 int ret;
347
Patrick Delaunay0d5fbad2020-11-06 19:01:51 +0100348 dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
Patrick Delaunaye1904ab2019-03-29 15:42:12 +0100349 if (usbphyc_phy->vdd) {
350 ret = regulator_set_enable(usbphyc_phy->vdd, true);
Patrice Chotard3b291212018-04-27 11:01:55 +0200351 if (ret)
352 return ret;
353 }
Patrick Delaunayc4801382020-10-15 14:50:57 +0200354 if (usbphyc_phy->vbus) {
355 ret = regulator_set_enable(usbphyc_phy->vbus, true);
356 if (ret)
357 return ret;
358 }
Patrice Chotard3b291212018-04-27 11:01:55 +0200359
360 usbphyc_phy->powered = true;
361
362 return 0;
363}
364
365static int stm32_usbphyc_phy_power_off(struct phy *phy)
366{
367 struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
368 struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
369 int ret;
370
Patrick Delaunay0d5fbad2020-11-06 19:01:51 +0100371 dev_dbg(phy->dev, "phy ID = %lu\n", phy->id);
Patrice Chotard3b291212018-04-27 11:01:55 +0200372 usbphyc_phy->powered = false;
373
374 if (stm32_usbphyc_is_powered(usbphyc))
375 return 0;
376
Patrick Delaunayc4801382020-10-15 14:50:57 +0200377 if (usbphyc_phy->vbus) {
Patrick Delaunay91dae6d2022-09-20 13:39:56 +0200378 ret = regulator_set_enable_if_allowed(usbphyc_phy->vbus, false);
Patrick Delaunayc4801382020-10-15 14:50:57 +0200379 if (ret)
380 return ret;
381 }
Patrick Delaunaye1904ab2019-03-29 15:42:12 +0100382 if (usbphyc_phy->vdd) {
Patrick Delaunay9f9191a2020-07-03 19:13:02 +0200383 ret = regulator_set_enable_if_allowed(usbphyc_phy->vdd, false);
Patrice Chotard3b291212018-04-27 11:01:55 +0200384 if (ret)
385 return ret;
386 }
387
388 return 0;
389}
390
Patrick Delaunayc4801382020-10-15 14:50:57 +0200391static int stm32_usbphyc_get_regulator(ofnode node,
Patrice Chotard3b291212018-04-27 11:01:55 +0200392 char *supply_name,
393 struct udevice **regulator)
394{
395 struct ofnode_phandle_args regulator_phandle;
396 int ret;
397
398 ret = ofnode_parse_phandle_with_args(node, supply_name,
399 NULL, 0, 0,
400 &regulator_phandle);
Patrick Delaunayc4801382020-10-15 14:50:57 +0200401 if (ret)
Patrice Chotard3b291212018-04-27 11:01:55 +0200402 return ret;
Patrice Chotard3b291212018-04-27 11:01:55 +0200403
404 ret = uclass_get_device_by_ofnode(UCLASS_REGULATOR,
405 regulator_phandle.node,
406 regulator);
Patrick Delaunayc4801382020-10-15 14:50:57 +0200407 if (ret)
Patrice Chotard3b291212018-04-27 11:01:55 +0200408 return ret;
Patrice Chotard3b291212018-04-27 11:01:55 +0200409
410 return 0;
411}
412
413static int stm32_usbphyc_of_xlate(struct phy *phy,
414 struct ofnode_phandle_args *args)
415{
Patrick Delaunay1655f2d2019-03-29 15:42:10 +0100416 if (args->args_count < 1)
417 return -ENODEV;
Patrice Chotard3b291212018-04-27 11:01:55 +0200418
419 if (args->args[0] >= MAX_PHYS)
420 return -ENODEV;
421
Patrick Delaunay1655f2d2019-03-29 15:42:10 +0100422 phy->id = args->args[0];
423
424 if ((phy->id == 0 && args->args_count != 1) ||
425 (phy->id == 1 && args->args_count != 2)) {
Sean Anderson0aeaca62020-09-15 10:45:06 -0400426 dev_err(phy->dev, "invalid number of cells for phy port%ld\n",
Patrick Delaunay1655f2d2019-03-29 15:42:10 +0100427 phy->id);
428 return -EINVAL;
429 }
Patrice Chotard3b291212018-04-27 11:01:55 +0200430
431 return 0;
432}
433
Patrice Chotardda6473c2022-04-22 09:39:00 +0200434static void stm32_usbphyc_tuning(struct udevice *dev, ofnode node, u32 index)
435{
436 struct stm32_usbphyc *usbphyc = dev_get_priv(dev);
437 u32 reg = STM32_USBPHYC_TUNE(index);
438 u32 otpcomp, val, tune = 0;
439 int ret;
440
441 /* Backup OTP compensation code */
442 otpcomp = FIELD_GET(OTPCOMP, readl(usbphyc->base + reg));
443
444 ret = ofnode_read_u32(node, "st,current-boost-microamp", &val);
445 if (!ret && (val == BOOST_1000_UA || val == BOOST_2000_UA)) {
446 val = (val == BOOST_2000_UA) ? 1 : 0;
447 tune |= INCURREN | FIELD_PREP(INCURRINT, val);
448 } else if (ret != -EINVAL) {
449 dev_warn(dev, "phy%d: invalid st,current-boost-microamp value\n", index);
450 }
451
452 if (!ofnode_read_bool(node, "st,no-lsfs-fb-cap"))
453 tune |= LFSCAPEN;
454
455 if (ofnode_read_bool(node, "st,decrease-hs-slew-rate"))
456 tune |= HSDRVSLEW;
457
458 ret = ofnode_read_u32(node, "st,tune-hs-dc-level", &val);
459 if (!ret && val < DC_MAX) {
460 if (val == DC_MINUS_5_TO_7_MV) {
461 tune |= HSDRVDCCUR;
462 } else {
463 val = (val == DC_PLUS_10_TO_14_MV) ? 1 : 0;
464 tune |= HSDRVCURINCR | FIELD_PREP(HSDRVDCLEV, val);
465 }
466 } else if (ret != -EINVAL) {
467 dev_warn(dev, "phy%d: invalid st,tune-hs-dc-level value\n", index);
468 }
469
470 if (ofnode_read_bool(node, "st,enable-fs-rftime-tuning"))
471 tune |= FSDRVRFADJ;
472
473 if (ofnode_read_bool(node, "st,enable-hs-rftime-reduction"))
474 tune |= HSDRVRFRED;
475
476 ret = ofnode_read_u32(node, "st,trim-hs-current", &val);
477 if (!ret && val < CUR_MAX)
478 tune |= FIELD_PREP(HSDRVCHKITRM, val);
479 else if (ret != -EINVAL)
480 dev_warn(dev, "phy%d: invalid st,trim-hs-current value\n", index);
481
482 ret = ofnode_read_u32(node, "st,trim-hs-impedance", &val);
483 if (!ret && val < IMP_MAX)
484 tune |= FIELD_PREP(HSDRVCHKZTRM, val);
485 else if (ret != -EINVAL)
486 dev_warn(dev, "phy%d: invalid trim-hs-impedance value\n", index);
487
488 ret = ofnode_read_u32(node, "st,tune-squelch-level", &val);
489 if (!ret && val < SQLCH_MAX)
490 tune |= FIELD_PREP(SQLCHCTL, val);
491 else if (ret != -EINVAL)
492 dev_warn(dev, "phy%d: invalid st,tune-squelch-level value\n", index);
493
494 if (ofnode_read_bool(node, "st,enable-hs-rx-gain-eq"))
495 tune |= HDRXGNEQEN;
496
497 ret = ofnode_read_u32(node, "st,tune-hs-rx-offset", &val);
498 if (!ret && val < RX_OFFSET_MAX)
499 tune |= FIELD_PREP(HSRXOFF, val);
500 else if (ret != -EINVAL)
501 dev_warn(dev, "phy%d: invalid st,tune-hs-rx-offset value\n", index);
502
503 if (ofnode_read_bool(node, "st,no-hs-ftime-ctrl"))
504 tune |= HSFALLPREEM;
505
506 if (!ofnode_read_bool(node, "st,no-lsfs-sc"))
507 tune |= SHTCCTCTLPROT;
508
509 if (ofnode_read_bool(node, "st,enable-hs-tx-staggering"))
510 tune |= STAGSEL;
511
512 /* Restore OTP compensation code */
513 tune |= FIELD_PREP(OTPCOMP, otpcomp);
514
515 writel(tune, usbphyc->base + reg);
516}
517
Patrice Chotard3b291212018-04-27 11:01:55 +0200518static const struct phy_ops stm32_usbphyc_phy_ops = {
519 .init = stm32_usbphyc_phy_init,
520 .exit = stm32_usbphyc_phy_exit,
521 .power_on = stm32_usbphyc_phy_power_on,
522 .power_off = stm32_usbphyc_phy_power_off,
523 .of_xlate = stm32_usbphyc_of_xlate,
524};
525
Patrick Delaunay9406f972022-04-26 14:37:48 +0200526static int stm32_usbphyc_bind(struct udevice *dev)
527{
528 int ret;
529
530 ret = device_bind_driver_to_node(dev, "stm32-usbphyc-clk", "ck_usbo_48m",
531 dev_ofnode(dev), NULL);
532
533 return log_ret(ret);
534}
535
Patrice Chotard3b291212018-04-27 11:01:55 +0200536static int stm32_usbphyc_probe(struct udevice *dev)
537{
538 struct stm32_usbphyc *usbphyc = dev_get_priv(dev);
539 struct reset_ctl reset;
Patrick Delaunay5b4fa852021-09-14 14:31:16 +0200540 ofnode node, connector;
Patrick Delaunay5d816162021-09-14 14:31:17 +0200541 int ret;
Patrice Chotard3b291212018-04-27 11:01:55 +0200542
543 usbphyc->base = dev_read_addr(dev);
544 if (usbphyc->base == FDT_ADDR_T_NONE)
545 return -EINVAL;
546
547 /* Enable clock */
548 ret = clk_get_by_index(dev, 0, &usbphyc->clk);
549 if (ret)
550 return ret;
551
552 ret = clk_enable(&usbphyc->clk);
553 if (ret)
554 return ret;
555
556 /* Reset */
557 ret = reset_get_by_index(dev, 0, &reset);
558 if (!ret) {
559 reset_assert(&reset);
560 udelay(2);
561 reset_deassert(&reset);
562 }
563
Patrick Delaunayc50151d2019-03-29 15:42:11 +0100564 /* get usbphyc regulator */
565 ret = device_get_supply_regulator(dev, "vdda1v1-supply",
566 &usbphyc->vdda1v1);
567 if (ret) {
568 dev_err(dev, "Can't get vdda1v1-supply regulator\n");
569 return ret;
570 }
571
572 ret = device_get_supply_regulator(dev, "vdda1v8-supply",
573 &usbphyc->vdda1v8);
574 if (ret) {
575 dev_err(dev, "Can't get vdda1v8-supply regulator\n");
576 return ret;
577 }
578
Patrick Delaunay5d816162021-09-14 14:31:17 +0200579 /* parse all PHY subnodes to populate regulator associated to each PHY port */
580 dev_for_each_subnode(node, dev) {
581 fdt_addr_t phy_id;
582 struct stm32_usbphyc_phy *usbphyc_phy;
Patrice Chotard3b291212018-04-27 11:01:55 +0200583
Patrick Delaunay5d816162021-09-14 14:31:17 +0200584 phy_id = ofnode_read_u32_default(node, "reg", FDT_ADDR_T_NONE);
585 if (phy_id >= MAX_PHYS) {
586 dev_err(dev, "invalid reg value %lx for %s\n",
587 phy_id, ofnode_get_name(node));
588 return -ENOENT;
589 }
Patrice Chotardda6473c2022-04-22 09:39:00 +0200590
591 /* Configure phy tuning */
592 stm32_usbphyc_tuning(dev, node, phy_id);
593
Patrick Delaunay5d816162021-09-14 14:31:17 +0200594 usbphyc_phy = usbphyc->phys + phy_id;
Patrice Chotard3b291212018-04-27 11:01:55 +0200595 usbphyc_phy->init = false;
596 usbphyc_phy->powered = false;
Patrick Delaunayc4801382020-10-15 14:50:57 +0200597 ret = stm32_usbphyc_get_regulator(node, "phy-supply",
Patrice Chotard3b291212018-04-27 11:01:55 +0200598 &usbphyc_phy->vdd);
Patrick Delaunayc4801382020-10-15 14:50:57 +0200599 if (ret) {
600 dev_err(dev, "Can't get phy-supply regulator\n");
Patrice Chotard3b291212018-04-27 11:01:55 +0200601 return ret;
Patrick Delaunayc4801382020-10-15 14:50:57 +0200602 }
603
Patrick Delaunay5b4fa852021-09-14 14:31:16 +0200604 usbphyc_phy->vbus = NULL;
605 connector = ofnode_find_subnode(node, "connector");
606 if (ofnode_valid(connector)) {
607 ret = stm32_usbphyc_get_regulator(connector, "vbus-supply",
608 &usbphyc_phy->vbus);
609 }
Patrice Chotard3b291212018-04-27 11:01:55 +0200610 }
611
612 /* Check if second port has to be used for host controller */
613 if (dev_read_bool(dev, "st,port2-switch-to-host"))
614 setbits_le32(usbphyc->base + STM32_USBPHYC_MISC, SWITHOST);
615
616 return 0;
617}
618
619static const struct udevice_id stm32_usbphyc_of_match[] = {
620 { .compatible = "st,stm32mp1-usbphyc", },
621 { },
622};
623
624U_BOOT_DRIVER(stm32_usb_phyc) = {
625 .name = "stm32-usbphyc",
626 .id = UCLASS_PHY,
627 .of_match = stm32_usbphyc_of_match,
628 .ops = &stm32_usbphyc_phy_ops,
Patrick Delaunay9406f972022-04-26 14:37:48 +0200629 .bind = stm32_usbphyc_bind,
Patrice Chotard3b291212018-04-27 11:01:55 +0200630 .probe = stm32_usbphyc_probe,
Simon Glass41575d82020-12-03 16:55:17 -0700631 .priv_auto = sizeof(struct stm32_usbphyc),
Patrice Chotard3b291212018-04-27 11:01:55 +0200632};
Patrick Delaunay9406f972022-04-26 14:37:48 +0200633
634struct stm32_usbphyc_clk {
635 bool enable;
636};
637
638static ulong stm32_usbphyc_clk48_get_rate(struct clk *clk)
639{
640 return USBPHYC_CLK48_FREQ;
641}
642
643static int stm32_usbphyc_clk48_enable(struct clk *clk)
644{
645 struct stm32_usbphyc_clk *usbphyc_clk = dev_get_priv(clk->dev);
646 struct stm32_usbphyc *usbphyc;
647 int ret;
648
649 if (usbphyc_clk->enable)
650 return 0;
651
652 usbphyc = dev_get_priv(clk->dev->parent);
653
654 /* ck_usbo_48m is generated by usbphyc PLL */
655 ret = stm32_usbphyc_pll_enable(usbphyc);
656 if (ret)
657 return ret;
658
659 usbphyc_clk->enable = true;
660
661 return 0;
662}
663
664static int stm32_usbphyc_clk48_disable(struct clk *clk)
665{
666 struct stm32_usbphyc_clk *usbphyc_clk = dev_get_priv(clk->dev);
667 struct stm32_usbphyc *usbphyc;
668 int ret;
669
670 if (!usbphyc_clk->enable)
671 return 0;
672
673 usbphyc = dev_get_priv(clk->dev->parent);
674
675 ret = stm32_usbphyc_pll_disable(usbphyc);
676 if (ret)
677 return ret;
678
679 usbphyc_clk->enable = false;
680
681 return 0;
682}
683
684const struct clk_ops usbphyc_clk48_ops = {
685 .get_rate = stm32_usbphyc_clk48_get_rate,
686 .enable = stm32_usbphyc_clk48_enable,
687 .disable = stm32_usbphyc_clk48_disable,
688};
689
690U_BOOT_DRIVER(stm32_usb_phyc_clk) = {
691 .name = "stm32-usbphyc-clk",
692 .id = UCLASS_CLK,
693 .ops = &usbphyc_clk48_ops,
694 .priv_auto = sizeof(struct stm32_usbphyc_clk),
695};