blob: 52942edbd416986c3a37072a7a283668af5b546f [file] [log] [blame]
Shengzhou Liuaba80042014-11-24 17:11:55 +08001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7/*
8 * T1024/T1023 QDS board configuration file
9 */
10
11#ifndef __T1024QDS_H
12#define __T1024QDS_H
13
14/* High Level Configuration Options */
Shengzhou Liuaba80042014-11-24 17:11:55 +080015#define CONFIG_DISPLAY_BOARDINFO
16#define CONFIG_BOOKE
17#define CONFIG_E500 /* BOOKE e500 family */
18#define CONFIG_E500MC /* BOOKE e500mc family */
19#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
20#define CONFIG_MP /* support multiple processors */
21#define CONFIG_PHYS_64BIT
22#define CONFIG_ENABLE_36BIT_PHYS
23
24#ifdef CONFIG_PHYS_64BIT
25#define CONFIG_ADDR_MAP 1
26#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
27#endif
28
29#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
30#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
31#define CONFIG_FSL_IFC /* Enable IFC Support */
32
33#define CONFIG_FSL_LAW /* Use common FSL init code */
34#define CONFIG_ENV_OVERWRITE
35
36#define CONFIG_DEEP_SLEEP
tang yuantian2c537642014-12-18 09:55:07 +080037#if defined(CONFIG_DEEP_SLEEP)
Shengzhou Liuaba80042014-11-24 17:11:55 +080038#define CONFIG_SILENT_CONSOLE
tang yuantian2c537642014-12-18 09:55:07 +080039#define CONFIG_BOARD_EARLY_INIT_F
40#endif
Shengzhou Liuaba80042014-11-24 17:11:55 +080041
42#ifdef CONFIG_RAMBOOT_PBL
43#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
44#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_rcw.cfg
45#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
46#define CONFIG_SPL_ENV_SUPPORT
47#define CONFIG_SPL_SERIAL_SUPPORT
48#define CONFIG_SPL_FLUSH_IMAGE
49#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
50#define CONFIG_SPL_LIBGENERIC_SUPPORT
51#define CONFIG_SPL_LIBCOMMON_SUPPORT
52#define CONFIG_SPL_I2C_SUPPORT
53#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
54#define CONFIG_FSL_LAW /* Use common FSL init code */
55#define CONFIG_SYS_TEXT_BASE 0x00201000
56#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
57#define CONFIG_SPL_PAD_TO 0x40000
58#define CONFIG_SPL_MAX_SIZE 0x28000
59#define RESET_VECTOR_OFFSET 0x27FFC
60#define BOOT_PAGE_OFFSET 0x27000
61#ifdef CONFIG_SPL_BUILD
62#define CONFIG_SPL_SKIP_RELOCATE
63#define CONFIG_SPL_COMMON_INIT_DDR
64#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
65#define CONFIG_SYS_NO_FLASH
66#endif
67
68#ifdef CONFIG_NAND
69#define CONFIG_SPL_NAND_SUPPORT
70#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
71#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
72#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
73#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
74#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
75#define CONFIG_SPL_NAND_BOOT
76#endif
77
78#ifdef CONFIG_SPIFLASH
79#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
80#define CONFIG_SPL_SPI_SUPPORT
81#define CONFIG_SPL_SPI_FLASH_SUPPORT
82#define CONFIG_SPL_SPI_FLASH_MINIMAL
83#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
84#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
85#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
86#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
87#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
88#ifndef CONFIG_SPL_BUILD
89#define CONFIG_SYS_MPC85XX_NO_RESETVEC
90#endif
91#define CONFIG_SPL_SPI_BOOT
92#endif
93
94#ifdef CONFIG_SDCARD
95#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
96#define CONFIG_SPL_MMC_SUPPORT
97#define CONFIG_SPL_MMC_MINIMAL
98#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
99#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
100#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
101#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
102#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
103#ifndef CONFIG_SPL_BUILD
104#define CONFIG_SYS_MPC85XX_NO_RESETVEC
105#endif
106#define CONFIG_SPL_MMC_BOOT
107#endif
108
109#endif /* CONFIG_RAMBOOT_PBL */
110
111#ifndef CONFIG_SYS_TEXT_BASE
112#define CONFIG_SYS_TEXT_BASE 0xeff40000
113#endif
114
115#ifndef CONFIG_RESET_VECTOR_ADDRESS
116#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
117#endif
118
119#ifndef CONFIG_SYS_NO_FLASH
120#define CONFIG_FLASH_CFI_DRIVER
121#define CONFIG_SYS_FLASH_CFI
122#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
123#endif
124
125/* PCIe Boot - Master */
126#define CONFIG_SRIO_PCIE_BOOT_MASTER
127/*
128 * for slave u-boot IMAGE instored in master memory space,
129 * PHYS must be aligned based on the SIZE
130 */
131#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
132#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
133#ifdef CONFIG_PHYS_64BIT
134#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
135#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
136#else
137#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
138#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
139#endif
140/*
141 * for slave UCODE and ENV instored in master memory space,
142 * PHYS must be aligned based on the SIZE
143 */
144#ifdef CONFIG_PHYS_64BIT
145#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
146#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
147#else
148#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
149#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
150#endif
151#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
152/* slave core release by master*/
153#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
154#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
155
156/* PCIe Boot - Slave */
157#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
158#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
159#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
160 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
161/* Set 1M boot space for PCIe boot */
162#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
163#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
164 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
165#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
166#define CONFIG_SYS_NO_FLASH
167#endif
168
169#if defined(CONFIG_SPIFLASH)
170#define CONFIG_SYS_EXTRA_ENV_RELOC
171#define CONFIG_ENV_IS_IN_SPI_FLASH
172#define CONFIG_ENV_SPI_BUS 0
173#define CONFIG_ENV_SPI_CS 0
174#define CONFIG_ENV_SPI_MAX_HZ 10000000
175#define CONFIG_ENV_SPI_MODE 0
176#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
177#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
178#define CONFIG_ENV_SECT_SIZE 0x10000
179#elif defined(CONFIG_SDCARD)
180#define CONFIG_SYS_EXTRA_ENV_RELOC
181#define CONFIG_ENV_IS_IN_MMC
182#define CONFIG_SYS_MMC_ENV_DEV 0
183#define CONFIG_ENV_SIZE 0x2000
184#define CONFIG_ENV_OFFSET (512 * 0x800)
185#elif defined(CONFIG_NAND)
186#define CONFIG_SYS_EXTRA_ENV_RELOC
187#define CONFIG_ENV_IS_IN_NAND
188#define CONFIG_ENV_SIZE 0x2000
189#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
190#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
191#define CONFIG_ENV_IS_IN_REMOTE
192#define CONFIG_ENV_ADDR 0xffe20000
193#define CONFIG_ENV_SIZE 0x2000
194#elif defined(CONFIG_ENV_IS_NOWHERE)
195#define CONFIG_ENV_SIZE 0x2000
196#else
197#define CONFIG_ENV_IS_IN_FLASH
198#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
199#define CONFIG_ENV_SIZE 0x2000
200#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
201#endif
202
203
204#ifndef __ASSEMBLY__
205unsigned long get_board_sys_clk(void);
206unsigned long get_board_ddr_clk(void);
207#endif
208
209#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
210#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
211
212/*
213 * These can be toggled for performance analysis, otherwise use default.
214 */
215#define CONFIG_SYS_CACHE_STASHING
216#define CONFIG_BACKSIDE_L2_CACHE
217#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
218#define CONFIG_BTB /* toggle branch predition */
219#define CONFIG_DDR_ECC
220#ifdef CONFIG_DDR_ECC
221#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
222#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
223#endif
224
225#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
226#define CONFIG_SYS_MEMTEST_END 0x00400000
227#define CONFIG_SYS_ALT_MEMTEST
228#define CONFIG_PANIC_HANG /* do not reset board on panic */
229
230/*
231 * Config the L3 Cache as L3 SRAM
232 */
233#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
234#define CONFIG_SYS_L3_SIZE (256 << 10)
235#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
236#ifdef CONFIG_RAMBOOT_PBL
237#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
238#endif
239#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
240#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
241#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
242#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
243
244#ifdef CONFIG_PHYS_64BIT
245#define CONFIG_SYS_DCSRBAR 0xf0000000
246#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
247#endif
248
249/* EEPROM */
250#define CONFIG_ID_EEPROM
251#define CONFIG_SYS_I2C_EEPROM_NXID
252#define CONFIG_SYS_EEPROM_BUS_NUM 0
253#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
254#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
255#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
256#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
257
258/*
259 * DDR Setup
260 */
261#define CONFIG_VERY_BIG_RAM
262#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
263#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
264#define CONFIG_DIMM_SLOTS_PER_CTLR 1
265#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
266#define CONFIG_DDR_SPD
267#ifndef CONFIG_SYS_FSL_DDR4
268#define CONFIG_SYS_FSL_DDR3
269#endif
270
271#define CONFIG_SYS_SPD_BUS_NUM 0
272#define SPD_EEPROM_ADDRESS 0x51
273
274#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
275
276/*
277 * IFC Definitions
278 */
279#define CONFIG_SYS_FLASH_BASE 0xe0000000
280#ifdef CONFIG_PHYS_64BIT
281#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
282#else
283#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
284#endif
285
286#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
287#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
288 + 0x8000000) | \
289 CSPR_PORT_SIZE_16 | \
290 CSPR_MSEL_NOR | \
291 CSPR_V)
292#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
293#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
294 CSPR_PORT_SIZE_16 | \
295 CSPR_MSEL_NOR | \
296 CSPR_V)
297#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
298/* NOR Flash Timing Params */
299#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
300#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
301 FTIM0_NOR_TEADC(0x5) | \
302 FTIM0_NOR_TEAHC(0x5))
303#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
304 FTIM1_NOR_TRAD_NOR(0x1A) |\
305 FTIM1_NOR_TSEQRAD_NOR(0x13))
306#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
307 FTIM2_NOR_TCH(0x4) | \
308 FTIM2_NOR_TWPH(0x0E) | \
309 FTIM2_NOR_TWP(0x1c))
310#define CONFIG_SYS_NOR_FTIM3 0x0
311
312#define CONFIG_SYS_FLASH_QUIET_TEST
313#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
314
315#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
316#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
317#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
318#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
319
320#define CONFIG_SYS_FLASH_EMPTY_INFO
321#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
322 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
323#define CONFIG_FSL_QIXIS /* use common QIXIS code */
324#define QIXIS_BASE 0xffdf0000
325#ifdef CONFIG_PHYS_64BIT
326#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
327#else
328#define QIXIS_BASE_PHYS QIXIS_BASE
329#endif
330#define QIXIS_LBMAP_SWITCH 0x06
331#define QIXIS_LBMAP_MASK 0x0f
332#define QIXIS_LBMAP_SHIFT 0
333#define QIXIS_LBMAP_DFLTBANK 0x00
334#define QIXIS_LBMAP_ALTBANK 0x04
335#define QIXIS_RST_CTL_RESET 0x31
336#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
337#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
338#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
339#define QIXIS_RST_FORCE_MEM 0x01
340
341#define CONFIG_SYS_CSPR3_EXT (0xf)
342#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
343 | CSPR_PORT_SIZE_8 \
344 | CSPR_MSEL_GPCM \
345 | CSPR_V)
346#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
347#define CONFIG_SYS_CSOR3 0x0
348/* QIXIS Timing parameters for IFC CS3 */
349#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
350 FTIM0_GPCM_TEADC(0x0e) | \
351 FTIM0_GPCM_TEAHC(0x0e))
352#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
353 FTIM1_GPCM_TRAD(0x3f))
354#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
355 FTIM2_GPCM_TCH(0x8) | \
356 FTIM2_GPCM_TWP(0x1f))
357#define CONFIG_SYS_CS3_FTIM3 0x0
358
359#define CONFIG_NAND_FSL_IFC
360#define CONFIG_SYS_NAND_BASE 0xff800000
361#ifdef CONFIG_PHYS_64BIT
362#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
363#else
364#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
365#endif
366#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
367#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
368 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
369 | CSPR_MSEL_NAND /* MSEL = NAND */ \
370 | CSPR_V)
371#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
372
373#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
374 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
375 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
376 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
377 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
378 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
379 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
380
381#define CONFIG_SYS_NAND_ONFI_DETECTION
382
383/* ONFI NAND Flash mode0 Timing Params */
384#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
385 FTIM0_NAND_TWP(0x18) | \
386 FTIM0_NAND_TWCHT(0x07) | \
387 FTIM0_NAND_TWH(0x0a))
388#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
389 FTIM1_NAND_TWBE(0x39) | \
390 FTIM1_NAND_TRR(0x0e) | \
391 FTIM1_NAND_TRP(0x18))
392#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
393 FTIM2_NAND_TREH(0x0a) | \
394 FTIM2_NAND_TWHRE(0x1e))
395#define CONFIG_SYS_NAND_FTIM3 0x0
396
397#define CONFIG_SYS_NAND_DDR_LAW 11
398#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
399#define CONFIG_SYS_MAX_NAND_DEVICE 1
Shengzhou Liuaba80042014-11-24 17:11:55 +0800400#define CONFIG_CMD_NAND
401
402#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
403
404#if defined(CONFIG_NAND)
405#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
406#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
407#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
408#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
409#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
410#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
411#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
412#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
413#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
414#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
415#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
416#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
417#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
418#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
419#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
420#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
421#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
422#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
423#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
424#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
425#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
426#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
427#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
428#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
429#else
430#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
431#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
432#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
433#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
434#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
435#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
436#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
437#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
438#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
439#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
440#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
441#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
442#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
443#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
444#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
445#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
446#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
447#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
448#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
449#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
450#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
451#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
452#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
453#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
454#endif
455
456#ifdef CONFIG_SPL_BUILD
457#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
458#else
459#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
460#endif
461
462#if defined(CONFIG_RAMBOOT_PBL)
463#define CONFIG_SYS_RAMBOOT
464#endif
465
466#define CONFIG_BOARD_EARLY_INIT_R
467#define CONFIG_MISC_INIT_R
468
469#define CONFIG_HWCONFIG
470
471/* define to use L1 as initial stack */
472#define CONFIG_L1_INIT_RAM
473#define CONFIG_SYS_INIT_RAM_LOCK
474#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
475#ifdef CONFIG_PHYS_64BIT
476#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
York Sunb3142e22015-08-17 13:31:51 -0700477#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
Shengzhou Liuaba80042014-11-24 17:11:55 +0800478/* The assembler doesn't like typecast */
479#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
480 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
481 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
482#else
York Sunb3142e22015-08-17 13:31:51 -0700483#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
Shengzhou Liuaba80042014-11-24 17:11:55 +0800484#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
485#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
486#endif
487#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
488
489#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
490 GENERATED_GBL_DATA_SIZE)
491#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
492
493#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
494#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
495
496/* Serial Port */
497#define CONFIG_CONS_INDEX 1
498#define CONFIG_SYS_NS16550
499#define CONFIG_SYS_NS16550_SERIAL
500#define CONFIG_SYS_NS16550_REG_SIZE 1
501#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
502
503#define CONFIG_SYS_BAUDRATE_TABLE \
504 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
505
506#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
507#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
508#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
509#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
510#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
511
512/* Use the HUSH parser */
513#define CONFIG_SYS_HUSH_PARSER
514#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
515
516/* Video */
517#ifdef CONFIG_PPC_T1024 /* no DIU on T1023 */
518#define CONFIG_FSL_DIU_FB
519#ifdef CONFIG_FSL_DIU_FB
520#define CONFIG_FSL_DIU_CH7301
521#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
522#define CONFIG_VIDEO
523#define CONFIG_CMD_BMP
524#define CONFIG_CFB_CONSOLE
525#define CONFIG_VIDEO_SW_CURSOR
526#define CONFIG_VGA_AS_SINGLE_DEVICE
527#define CONFIG_VIDEO_LOGO
528#define CONFIG_VIDEO_BMP_LOGO
529#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
530/*
531 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
532 * disable empty flash sector detection, which is I/O-intensive.
533 */
534#undef CONFIG_SYS_FLASH_EMPTY_INFO
535#endif
536#endif
537
538/* pass open firmware flat tree */
539#define CONFIG_OF_LIBFDT
540#define CONFIG_OF_BOARD_SETUP
541#define CONFIG_OF_STDOUT_VIA_ALIAS
542
543/* new uImage format support */
544#define CONFIG_FIT
545#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
546
547/* I2C */
548#define CONFIG_SYS_I2C
549#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
550#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
551#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
552#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
553#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
554#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
555#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
556
557#define I2C_MUX_PCA_ADDR 0x77
558#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
Shengzhou Liu10227aa2014-11-24 17:18:28 +0800559#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
560#define I2C_RETIMER_ADDR 0x18
Shengzhou Liuaba80042014-11-24 17:11:55 +0800561
562/* I2C bus multiplexer */
563#define I2C_MUX_CH_DEFAULT 0x8
564#define I2C_MUX_CH_DIU 0xC
Shengzhou Liu10227aa2014-11-24 17:18:28 +0800565#define I2C_MUX_CH5 0xD
566#define I2C_MUX_CH7 0xF
Shengzhou Liuaba80042014-11-24 17:11:55 +0800567
568/* LDI/DVI Encoder for display */
569#define CONFIG_SYS_I2C_LDI_ADDR 0x38
570#define CONFIG_SYS_I2C_DVI_ADDR 0x75
571
572/*
573 * RTC configuration
574 */
575#define RTC
576#define CONFIG_RTC_DS3231 1
577#define CONFIG_SYS_I2C_RTC_ADDR 0x68
578
579/*
580 * eSPI - Enhanced SPI
581 */
582#define CONFIG_FSL_ESPI
Shengzhou Liuaba80042014-11-24 17:11:55 +0800583#define CONFIG_SPI_FLASH_STMICRO
584#ifndef CONFIG_SPL_BUILD
585#define CONFIG_SPI_FLASH_SST
586#define CONFIG_SPI_FLASH_EON
587#endif
588#define CONFIG_CMD_SF
589#define CONFIG_SPI_FLASH_BAR
590#define CONFIG_SF_DEFAULT_SPEED 10000000
591#define CONFIG_SF_DEFAULT_MODE 0
592
593/*
594 * General PCIe
595 * Memory space is mapped 1-1, but I/O space must start from 0.
596 */
597#define CONFIG_PCI /* Enable PCI/PCIE */
598#define CONFIG_PCIE1 /* PCIE controler 1 */
599#define CONFIG_PCIE2 /* PCIE controler 2 */
600#define CONFIG_PCIE3 /* PCIE controler 3 */
601#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
602#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
603#define CONFIG_PCI_INDIRECT_BRIDGE
604
605#ifdef CONFIG_PCI
606/* controller 1, direct to uli, tgtid 3, Base address 20000 */
607#ifdef CONFIG_PCIE1
608#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
609#ifdef CONFIG_PHYS_64BIT
610#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
611#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
612#else
613#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
614#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
615#endif
616#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
617#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
618#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
619#ifdef CONFIG_PHYS_64BIT
620#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
621#else
622#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
623#endif
624#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
625#endif
626
627/* controller 2, Slot 2, tgtid 2, Base address 201000 */
628#ifdef CONFIG_PCIE2
629#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
630#ifdef CONFIG_PHYS_64BIT
631#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
632#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
633#else
634#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
635#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
636#endif
637#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
638#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
639#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
640#ifdef CONFIG_PHYS_64BIT
641#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
642#else
643#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
644#endif
645#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
646#endif
647
648/* controller 3, Slot 1, tgtid 1, Base address 202000 */
649#ifdef CONFIG_PCIE3
650#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
651#ifdef CONFIG_PHYS_64BIT
652#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
653#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
654#else
655#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
656#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
657#endif
658#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
659#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
660#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
661#ifdef CONFIG_PHYS_64BIT
662#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
663#else
664#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
665#endif
666#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
667#endif
668
669#define CONFIG_PCI_PNP /* do pci plug-and-play */
Shengzhou Liuaba80042014-11-24 17:11:55 +0800670#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
671#define CONFIG_DOS_PARTITION
672#endif /* CONFIG_PCI */
673
674/*
675 *SATA
676 */
677#define CONFIG_FSL_SATA_V2
678#ifdef CONFIG_FSL_SATA_V2
679#define CONFIG_LIBATA
680#define CONFIG_FSL_SATA
681#define CONFIG_SYS_SATA_MAX_DEVICE 1
682#define CONFIG_SATA1
683#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
684#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
685#define CONFIG_LBA48
686#define CONFIG_CMD_SATA
687#define CONFIG_DOS_PARTITION
688#define CONFIG_CMD_EXT2
689#endif
690
691/*
692 * USB
693 */
694#define CONFIG_HAS_FSL_DR_USB
695
696#ifdef CONFIG_HAS_FSL_DR_USB
697#define CONFIG_USB_EHCI
698#define CONFIG_CMD_USB
699#define CONFIG_USB_STORAGE
700#define CONFIG_USB_EHCI_FSL
701#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
702#define CONFIG_CMD_EXT2
703#endif
704
705/*
706 * SDHC
707 */
708#define CONFIG_MMC
709#ifdef CONFIG_MMC
710#define CONFIG_FSL_ESDHC
711#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
712#define CONFIG_CMD_MMC
713#define CONFIG_GENERIC_MMC
714#define CONFIG_CMD_EXT2
715#define CONFIG_CMD_FAT
716#define CONFIG_DOS_PARTITION
717#endif
718
719/* Qman/Bman */
720#ifndef CONFIG_NOBQFMAN
721#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
Jeffrey Ladouceur2a8b3422014-12-03 18:08:43 -0500722#define CONFIG_SYS_BMAN_NUM_PORTALS 10
Shengzhou Liuaba80042014-11-24 17:11:55 +0800723#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
724#ifdef CONFIG_PHYS_64BIT
725#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
726#else
727#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
728#endif
729#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500730#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
731#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
732#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
733#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
734#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
735 CONFIG_SYS_BMAN_CENA_SIZE)
736#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
737#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Jeffrey Ladouceur2a8b3422014-12-03 18:08:43 -0500738#define CONFIG_SYS_QMAN_NUM_PORTALS 10
Shengzhou Liuaba80042014-11-24 17:11:55 +0800739#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
740#ifdef CONFIG_PHYS_64BIT
741#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
742#else
743#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
744#endif
745#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500746#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
747#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
748#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
749#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
750#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
751 CONFIG_SYS_QMAN_CENA_SIZE)
752#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
753#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Shengzhou Liuaba80042014-11-24 17:11:55 +0800754
755#define CONFIG_SYS_DPAA_FMAN
756
757#define CONFIG_QE
758#define CONFIG_U_QE
759/* Default address of microcode for the Linux FMan driver */
760#if defined(CONFIG_SPIFLASH)
761/*
762 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
763 * env, so we got 0x110000.
764 */
765#define CONFIG_SYS_QE_FW_IN_SPIFLASH
766#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
767#define CONFIG_SYS_QE_FW_ADDR 0x130000
768#elif defined(CONFIG_SDCARD)
769/*
770 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
771 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
772 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
773 */
774#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
775#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
776#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
777#elif defined(CONFIG_NAND)
778#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
779#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
780#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
781#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
782/*
783 * Slave has no ucode locally, it can fetch this from remote. When implementing
784 * in two corenet boards, slave's ucode could be stored in master's memory
785 * space, the address can be mapped from slave TLB->slave LAW->
786 * slave SRIO or PCIE outbound window->master inbound window->
787 * master LAW->the ucode address in master's memory space.
788 */
789#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
790#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
791#else
792#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
793#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
794#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
795#endif
796#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
797#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
798#endif /* CONFIG_NOBQFMAN */
799
800#ifdef CONFIG_SYS_DPAA_FMAN
801#define CONFIG_FMAN_ENET
802#define CONFIG_PHYLIB_10G
803#define CONFIG_PHY_VITESSE
804#define CONFIG_PHY_REALTEK
805#define CONFIG_PHY_TERANETICS
806#define RGMII_PHY1_ADDR 0x1
807#define RGMII_PHY2_ADDR 0x2
808#define SGMII_CARD_AQ_PHY_ADDR_S3 0x3
809#define SGMII_CARD_AQ_PHY_ADDR_S4 0x4
810#define SGMII_CARD_AQ_PHY_ADDR_S5 0x5
811#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
812#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
813#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
814#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
815#endif
816
817#ifdef CONFIG_FMAN_ENET
818#define CONFIG_MII /* MII PHY management */
819#define CONFIG_ETHPRIME "FM1@DTSEC4"
820#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
821#endif
822
823/*
824 * Dynamic MTD Partition support with mtdparts
825 */
826#ifndef CONFIG_SYS_NO_FLASH
827#define CONFIG_MTD_DEVICE
828#define CONFIG_MTD_PARTITIONS
829#define CONFIG_CMD_MTDPARTS
830#define CONFIG_FLASH_CFI_MTD
831#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
832 "spi0=spife110000.0"
833#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
834 "128k(dtb),96m(fs),-(user);"\
835 "fff800000.flash:2m(uboot),9m(kernel),"\
836 "128k(dtb),96m(fs),-(user);spife110000.0:" \
837 "2m(uboot),9m(kernel),128k(dtb),-(user)"
838#endif
839
840/*
841 * Environment
842 */
843#define CONFIG_LOADS_ECHO /* echo on for serial download */
844#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
845
846/*
847 * Command line configuration.
848 */
Shengzhou Liuaba80042014-11-24 17:11:55 +0800849#define CONFIG_CMD_DATE
850#define CONFIG_CMD_DHCP
851#define CONFIG_CMD_EEPROM
Shengzhou Liuaba80042014-11-24 17:11:55 +0800852#define CONFIG_CMD_ERRATA
853#define CONFIG_CMD_GREPENV
854#define CONFIG_CMD_IRQ
855#define CONFIG_CMD_I2C
856#define CONFIG_CMD_MII
857#define CONFIG_CMD_PING
858#define CONFIG_CMD_REGINFO
Shengzhou Liuaba80042014-11-24 17:11:55 +0800859
860#ifdef CONFIG_PCI
861#define CONFIG_CMD_PCI
Shengzhou Liuaba80042014-11-24 17:11:55 +0800862#endif
863
864/*
865 * Miscellaneous configurable options
866 */
867#define CONFIG_SYS_LONGHELP /* undef to save memory */
868#define CONFIG_CMDLINE_EDITING /* Command-line editing */
869#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
870#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Shengzhou Liuaba80042014-11-24 17:11:55 +0800871#ifdef CONFIG_CMD_KGDB
872#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
873#else
874#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
875#endif
876#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
877#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
878#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
879
880/*
881 * For booting Linux, the board info and command line data
882 * have to be in the first 64 MB of memory, since this is
883 * the maximum mapped by the Linux kernel during initialization.
884 */
885#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
886#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
887
888#ifdef CONFIG_CMD_KGDB
889#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
890#endif
891
892/*
893 * Environment Configuration
894 */
895#define CONFIG_ROOTPATH "/opt/nfsroot"
896#define CONFIG_BOOTFILE "uImage"
897#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
898#define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */
899#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
900#define CONFIG_BAUDRATE 115200
901#define __USB_PHY_TYPE utmi
902
903
904#define CONFIG_EXTRA_ENV_SETTINGS \
905 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \
906 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
907 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
908 "ramdiskfile=t1024qds/ramdisk.uboot\0" \
909 "fdtfile=t1024qds/t1024qds.dtb\0" \
910 "netdev=eth0\0" \
911 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
912 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
913 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
914 "tftpflash=tftpboot $loadaddr $uboot && " \
915 "protect off $ubootaddr +$filesize && " \
916 "erase $ubootaddr +$filesize && " \
917 "cp.b $loadaddr $ubootaddr $filesize && " \
918 "protect on $ubootaddr +$filesize && " \
919 "cmp.b $loadaddr $ubootaddr $filesize\0" \
920 "consoledev=ttyS0\0" \
921 "ramdiskaddr=2000000\0" \
922 "fdtaddr=d00000\0" \
923 "bdev=sda3\0"
924
925#define CONFIG_LINUX \
926 "setenv bootargs root=/dev/ram rw " \
927 "console=$consoledev,$baudrate $othbootargs;" \
928 "setenv ramdiskaddr 0x02000000;" \
929 "setenv fdtaddr 0x00c00000;" \
930 "setenv loadaddr 0x1000000;" \
931 "bootm $loadaddr $ramdiskaddr $fdtaddr"
932
933#define CONFIG_NFSBOOTCOMMAND \
934 "setenv bootargs root=/dev/nfs rw " \
935 "nfsroot=$serverip:$rootpath " \
936 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
937 "console=$consoledev,$baudrate $othbootargs;" \
938 "tftp $loadaddr $bootfile;" \
939 "tftp $fdtaddr $fdtfile;" \
940 "bootm $loadaddr - $fdtaddr"
941
942#define CONFIG_BOOTCOMMAND CONFIG_LINUX
943
944#ifdef CONFIG_SECURE_BOOT
945#include <asm/fsl_secure_boot.h>
946#endif
947
948#endif /* __T1024QDS_H */