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Aubrey Li65458982007-03-20 18:16:24 +08001/*
2 * U-boot - Configuration file for BF561 EZKIT board
3 */
4
Mike Frysingercf6f4692008-06-01 09:09:48 -04005#ifndef __CONFIG_BF561_EZKIT_H__
6#define __CONFIG_BF561_EZKIT_H__
Aubrey Li65458982007-03-20 18:16:24 +08007
Mike Frysingerf348ab82009-04-24 17:22:40 -04008#include <asm/config-pre.h>
Mike Frysingerf7ce12c2008-02-18 05:26:48 -05009
Aubrey Li65458982007-03-20 18:16:24 +080010
Aubrey Li65458982007-03-20 18:16:24 +080011/*
Mike Frysingercf6f4692008-06-01 09:09:48 -040012 * Processor Settings
Aubrey Li65458982007-03-20 18:16:24 +080013 */
Mike Frysingerfbcf8e82010-12-23 14:58:37 -050014#define CONFIG_BFIN_CPU bf561-0.3
Mike Frysingercf6f4692008-06-01 09:09:48 -040015#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
16
17
18/*
19 * Clock Settings
20 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
21 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
22 */
23/* CONFIG_CLKIN_HZ is any value in Hz */
24#define CONFIG_CLKIN_HZ 30000000
25/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
26/* 1 = CLKIN / 2 */
27#define CONFIG_CLKIN_HALF 0
28/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
29/* 1 = bypass PLL */
30#define CONFIG_PLL_BYPASS 0
31/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
32/* Values can range from 0-63 (where 0 means 64) */
33#define CONFIG_VCO_MULT 20
34/* CCLK_DIV controls the core clock divider */
35/* Values can be 1, 2, 4, or 8 ONLY */
36#define CONFIG_CCLK_DIV 1
37/* SCLK_DIV controls the system clock divider */
38/* Values can range from 1-15 */
39#define CONFIG_SCLK_DIV 6
40
41
42/*
43 * Memory Settings
44 */
45#define CONFIG_MEM_ADD_WDTH 9
46#define CONFIG_MEM_SIZE 64
47
48#define CONFIG_EBIU_SDRRC_VAL 0x306
49#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
50
51#define CONFIG_EBIU_AMGCTL_VAL 0x3F
52#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
53#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
54
55#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
56#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
57
58
59/*
60 * Network Settings
61 */
62#define ADI_CMDS_NETWORK 1
Ben Warren7194ab82009-10-04 22:37:03 -070063#define CONFIG_SMC91111 1
Aubrey Li65458982007-03-20 18:16:24 +080064#define CONFIG_SMC91111_BASE 0x2C010300
Aubrey Li65458982007-03-20 18:16:24 +080065#define CONFIG_SMC_USE_32_BIT 1
Mike Frysingercf6f4692008-06-01 09:09:48 -040066#define CONFIG_HOSTNAME bf561-ezkit
Mike Frysingercf6f4692008-06-01 09:09:48 -040067
Aubrey Li65458982007-03-20 18:16:24 +080068
69/*
Mike Frysingercf6f4692008-06-01 09:09:48 -040070 * Flash Settings
Aubrey Li65458982007-03-20 18:16:24 +080071 */
Mike Frysingercf6f4692008-06-01 09:09:48 -040072#define CONFIG_SYS_FLASH_CFI
73#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#define CONFIG_SYS_FLASH_CFI_AMD_RESET
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075#define CONFIG_SYS_FLASH_BASE 0x20000000
Mike Frysingercf6f4692008-06-01 09:09:48 -040076#define CONFIG_SYS_MAX_FLASH_BANKS 1
77#define CONFIG_SYS_MAX_FLASH_SECT 135
78/* The BF561-EZKIT uses a top boot flash */
79#define CONFIG_ENV_IS_IN_FLASH 1
Mike Frysinger1b48f122011-05-09 15:43:27 -040080#define CONFIG_ENV_OFFSET (0x800000 - CONFIG_ENV_SECT_SIZE)
Mike Frysingerd2ab7332010-12-23 18:07:01 -050081#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
Mike Frysinger1b48f122011-05-09 15:43:27 -040082#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
83#define CONFIG_ENV_SECT_SIZE 0x2000
Aubrey Li65458982007-03-20 18:16:24 +080084
Mike Frysingercf6f4692008-06-01 09:09:48 -040085
86/*
87 * I2C Settings
88 */
Heiko Schocherea818db2013-01-29 08:53:15 +010089#define CONFIG_SYS_I2C_SOFT
90#ifdef CONFIG_SYS_I2C_SOFT
Sonic Zhangfa88d882013-12-09 12:21:07 +080091#define CONFIG_SYS_I2C
Mike Frysingerbeb60e72010-06-08 16:22:44 -040092#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0
93#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1
Heiko Schocherea818db2013-01-29 08:53:15 +010094#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
95#define CONFIG_SYS_I2C_SOFT_SPEED 50000
96#define CONFIG_SYS_I2C_SOFT_SLAVE 0
97#endif
Aubrey Li65458982007-03-20 18:16:24 +080098
Jon Loeligerba2351f2007-07-04 22:31:49 -050099/*
Mike Frysingercf6f4692008-06-01 09:09:48 -0400100 * Misc Settings
Jon Loeliger079a1362007-07-10 10:12:10 -0500101 */
Mike Frysingercf6f4692008-06-01 09:09:48 -0400102#define CONFIG_UART_CONSOLE 0
103
Sonic Zhangf4d80382013-02-05 18:57:49 +0800104/*
105 * Run core 1 from L1 SRAM start address when init uboot on core 0
106 */
107/* #define CONFIG_CORE1_RUN 1 */
108
Jon Loeliger079a1362007-07-10 10:12:10 -0500109
Jon Loeliger079a1362007-07-10 10:12:10 -0500110/*
Mike Frysingercf6f4692008-06-01 09:09:48 -0400111 * Pull in common ADI header for remaining command/environment setup
Jon Loeligerba2351f2007-07-04 22:31:49 -0500112 */
Mike Frysingercf6f4692008-06-01 09:09:48 -0400113#include <configs/bfin_adi_common.h>
Aubrey Li65458982007-03-20 18:16:24 +0800114
Mike Frysingerf348ab82009-04-24 17:22:40 -0400115#endif