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wdenk16f21702002-08-26 21:58:50 +00001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <commproc.h>
26#include <mpc8xx.h>
27
28#ifdef CONFIG_SHOW_BOOT_PROGRESS
29# include <status_led.h>
Simon Glass770605e2012-02-13 13:51:18 +000030# define SHOW_BOOT_PROGRESS(arg) bootstage_mark(arg)
wdenk16f21702002-08-26 21:58:50 +000031#else
32# define SHOW_BOOT_PROGRESS(arg)
33#endif
34
Wolfgang Denkd87080b2006-03-31 18:32:53 +020035DECLARE_GLOBAL_DATA_PTR;
36
wdenk16f21702002-08-26 21:58:50 +000037/* ------------------------------------------------------------------------- */
38
39static long int dram_size (long int, long int *, long int);
40static ulong board_init (void);
41static void send_smi_frame (volatile scc_t * sp, volatile cbd_t * bd,
42 uchar * msg);
43
44/* ------------------------------------------------------------------------- */
45
46#define _NOT_USED_ 0xFFFFFFFF
47
48const uint sdram_table[] = {
49 /*
50 * Single Read. (Offset 0 in UPMA RAM)
51 */
52 0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
53 0x1ff77c47, /* last */
54 /*
55 * SDRAM Initialization (offset 5 in UPMA RAM)
56 *
57 * This is no UPM entry point. The following definition uses
58 * the remaining space to establish an initialization
59 * sequence, which is executed by a RUN command.
60 *
61 */
62 0x1fe77c35, 0xffaffc34, 0x1fa57c35, /* last */
63 /*
64 * Burst Read. (Offset 8 in UPMA RAM)
65 */
66 0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
67 0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, /* last */
68 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
69 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
70 /*
71 * Single Write. (Offset 18 in UPMA RAM)
72 */
73 0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, /* last */
74 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
75 /*
76 * Burst Write. (Offset 20 in UPMA RAM)
77 */
78 0x1f07fc04, 0xeeaebc00, 0x10ad4c00, 0xf0afcc00,
79 0xf0afcc00, 0xe1bb8c06, 0x1ff77c47, /* last */
80 _NOT_USED_,
81 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
82 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
83 /*
84 * Refresh (Offset 30 in UPMA RAM)
85 */
86 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
87 0xfffffc84, 0xfffffc07, /* last */
88 _NOT_USED_, _NOT_USED_,
89 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
90 /*
91 * Exception. (Offset 3c in UPMA RAM)
92 */
93 0x7ffffc07, /* last */
94 _NOT_USED_, _NOT_USED_, _NOT_USED_,
95};
96
97/* ------------------------------------------------------------------------- */
98
99
100/*
101 * Check Board Identity:
102 *
103 * Test ID string (HERMES...)
104 *
105 * Return code for board revision and network speed
106 */
107
108int checkboard (void)
109{
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +0000110 char buf[64];
111 int i;
112 int l = getenv_f("serial#", buf, sizeof(buf));
wdenk16f21702002-08-26 21:58:50 +0000113
114 puts ("Board: ");
115
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +0000116 if (l < 0 || strncmp(buf, "HERMES", 6)) {
wdenk16f21702002-08-26 21:58:50 +0000117 puts ("### No HW ID - assuming HERMES-PRO");
118 } else {
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +0000119 for (i = 0; i < l; i++) {
120 if (buf[i] == ' ')
wdenk16f21702002-08-26 21:58:50 +0000121 break;
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +0000122 putc (buf[i]);
wdenk16f21702002-08-26 21:58:50 +0000123 }
124 }
125
126 gd->board_type = board_init ();
127
128 printf (" Rev. %ld.x\n", (gd->board_type >> 16));
129
130 return (0);
131}
132
133/* ------------------------------------------------------------------------- */
134
Becky Bruce9973e3c2008-06-09 16:03:40 -0500135phys_size_t initdram (int board_type)
wdenk16f21702002-08-26 21:58:50 +0000136{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenk16f21702002-08-26 21:58:50 +0000138 volatile memctl8xx_t *memctl = &immap->im_memctl;
139 long int size, size8, size9;
140
141 upmconfig (UPMA, (uint *) sdram_table,
142 sizeof (sdram_table) / sizeof (uint));
143
144 /*
145 * Preliminary prescaler for refresh
146 */
147 memctl->memc_mptpr = 0x0400;
148
149 memctl->memc_mar = 0x00000088;
150
151 /*
152 * Map controller banks 1 to the SDRAM banks at preliminary address
153 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154 memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
155 memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
wdenk16f21702002-08-26 21:58:50 +0000156
157 /* HERMES-PRO boards have only one bank SDRAM */
158
159
160 udelay (200);
161
162 /* perform SDRAM initializsation sequence */
163
164 memctl->memc_mamr = 0xD0802114;
165 memctl->memc_mcr = 0x80002105;
166 udelay (1);
167 memctl->memc_mamr = 0xD0802118;
168 memctl->memc_mcr = 0x80002130;
169 udelay (1);
170 memctl->memc_mamr = 0xD0802114;
171 memctl->memc_mcr = 0x80002106;
172
173 udelay (1000);
174
175 /*
176 * Check Bank 0 Memory Size for re-configuration
177 *
178 * try 8 column mode
179 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180 size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE_PRELIM,
wdenk16f21702002-08-26 21:58:50 +0000181 SDRAM_MAX_SIZE);
182
183 udelay (1000);
184
185 /*
186 * try 9 column mode
187 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188 size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE_PRELIM,
wdenk16f21702002-08-26 21:58:50 +0000189 SDRAM_MAX_SIZE);
190
191 if (size8 < size9) { /* leave configuration at 9 columns */
192 size = size9;
193/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
194 } else { /* back to 8 columns */
195 size = size8;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196 memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
wdenk16f21702002-08-26 21:58:50 +0000197 udelay (500);
198/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
199 }
200
201 udelay (1000);
202
203 memctl->memc_or1 = ((-size) & 0xFFFF0000) | SDRAM_TIMING;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204 memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
wdenk16f21702002-08-26 21:58:50 +0000205
206 udelay (10000);
207
208 return (size);
209}
210
211/* ------------------------------------------------------------------------- */
212
213/*
214 * Check memory range for valid RAM. A simple memory test determines
215 * the actually available RAM size between addresses `base' and
216 * `base + maxsize'. Some (not all) hardware errors are detected:
217 * - short between address lines
218 * - short between data lines
219 */
220
221static long int dram_size (long int mamr_value, long int *base,
222 long int maxsize)
223{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
wdenk16f21702002-08-26 21:58:50 +0000225 volatile memctl8xx_t *memctl = &immap->im_memctl;
wdenk16f21702002-08-26 21:58:50 +0000226
227 memctl->memc_mamr = mamr_value;
228
wdenkc83bf6a2004-01-06 22:38:14 +0000229 return (get_ram_size(base, maxsize));
wdenk16f21702002-08-26 21:58:50 +0000230}
231
232/* ------------------------------------------------------------------------- */
233
234#define PB_LED_3 0x00020000 /* Status LED's */
235#define PB_LED_2 0x00010000
236#define PB_LED_1 0x00008000
237#define PB_LED_0 0x00004000
238
239#define PB_LED_ALL (PB_LED_0 | PB_LED_1 | PB_LED_2 | PB_LED_3)
240
241#define PC_REP_SPD1 0x00000800
242#define PC_REP_SPD0 0x00000400
243
244#define PB_RESET_2081 0x00000020 /* Reset PEB2081 */
245
246#define PB_MAI_4 0x00000010 /* Configuration */
247#define PB_MAI_3 0x00000008
248#define PB_MAI_2 0x00000004
249#define PB_MAI_1 0x00000002
250#define PB_MAI_0 0x00000001
251
252#define PB_MAI_ALL (PB_MAI_0 | PB_MAI_1 | PB_MAI_2 | PB_MAI_3 | PB_MAI_4)
253
254
255#define PC_REP_MGRPRS 0x0200
256#define PC_REP_SPD 0x0040 /* Select 100 Mbps */
257#define PC_REP_RES 0x0004
258#define PC_BIT14 0x0002 /* ??? */
259#define PC_BIT15 0x0001 /* ??? ENDSL ?? */
260
261/* ------------------------------------------------------------------------- */
262
263static ulong board_init (void)
264{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
wdenk16f21702002-08-26 21:58:50 +0000266 ulong reg, revision, speed = 100;
267 int ethspeed;
268 char *s;
269
270 if ((s = getenv ("ethspeed")) != NULL) {
271 if (strcmp (s, "100") == 0) {
272 ethspeed = 100;
273 } else if (strcmp (s, "10") == 0) {
274 ethspeed = 10;
275 } else {
276 ethspeed = 0;
277 }
278 } else {
279 ethspeed = 0;
280 }
281
282 /* Configure Port B Output Pins => 0x0003cc3F */
283 reg = PB_LED_ALL | PC_REP_SPD1 | PC_REP_SPD0 | PB_RESET_2081 |
284 PB_MAI_ALL;
285 immr->im_cpm.cp_pbpar &= ~reg;
286 immr->im_cpm.cp_pbodr &= ~reg;
287 immr->im_cpm.cp_pbdat &= ~reg; /* all 0 */
288 immr->im_cpm.cp_pbdir |= reg;
289
290 /* Check hardware revision */
291 if ((immr->im_ioport.iop_pcdat & 0x0003) == 0x0003) {
292 /*
293 * Revision 3.x hardware
294 */
295 revision = 3;
296
297 immr->im_ioport.iop_pcdat = 0x0240;
298 immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_SPD | PC_REP_RES | PC_BIT14); /* = 0x0246 */
299 immr->im_ioport.iop_pcdat |= PC_REP_RES;
300 } else {
301 immr->im_ioport.iop_pcdat = 0x0002;
302 immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_RES | PC_BIT14 | PC_BIT15); /* = 0x0207 */
303
304 if ((immr->im_ioport.iop_pcdat & PC_REP_SPD) == 0) {
305 /*
306 * Revision 2.x hardware: PC9 connected to PB21
307 */
308 revision = 2;
309
310 if (ethspeed == 0) {
311 /* both 10 and 100 Mbps allowed:
312 * select 10 Mbps and autonegotiation
313 */
314 puts (" [10+100]");
315 immr->im_cpm.cp_pbdat = 0; /* SPD1:SPD0 = 0:0 - autonegot. */
316 speed = 10;
317 } else if (ethspeed == 10) {
318 /* we are asked for 10 Mbps,
319 * so select 10 Mbps
320 */
321 puts (" [10]");
322 immr->im_cpm.cp_pbdat = 0; /* ??? */
323 speed = 10;
324 } else {
325 /* anything else:
326 * select 100 Mbps
327 */
328 puts (" [100]");
329 immr->im_cpm.cp_pbdat = PC_REP_SPD0 | PC_REP_SPD1;
330 /* SPD1:SPD0 = 1:1 - 100 Mbps */
331 speed = 100;
332 }
333 immr->im_ioport.iop_pcdat |= (PC_REP_RES | PC_BIT14);
334
335 /* must be run from RAM */
336 /* start_lxt980 (speed); */
337 /*************************/
338 } else {
339 /*
340 * Revision 1.x hardware
341 */
342 revision = 1;
343
344 immr->im_ioport.iop_pcdat = PC_REP_MGRPRS | PC_BIT14; /* = 0x0202 */
345 immr->im_ioport.iop_pcdir = (PC_REP_MGRPRS | PC_REP_SPD | PC_REP_RES | PC_BIT14 | PC_BIT15); /* = 0x0247 */
346
347 if (ethspeed == 0) {
348 /* both 10 and 100 Mbps allowed:
349 * select 100 Mbps and autonegotiation
350 */
351 puts (" [10+100]");
352 immr->im_cpm.cp_pbdat = 0; /* SPD1:SPD0 = 0:0 - autonegot. */
353 immr->im_ioport.iop_pcdat |= PC_REP_SPD;
354 } else if (ethspeed == 10) {
355 /* we are asked for 10 Mbps,
356 * so select 10 Mbps
357 */
358 puts (" [10]");
359 immr->im_cpm.cp_pbdat = PC_REP_SPD0; /* SPD1:SPD0 = 0:1 - 10 Mbps */
360 } else {
361 /* anything else:
362 * select 100 Mbps
363 */
364 puts (" [100]");
365 immr->im_cpm.cp_pbdat = PC_REP_SPD0 | PC_REP_SPD1;
366 /* SPD1:SPD0 = 1:1 - 100 Mbps */
367 immr->im_ioport.iop_pcdat |= PC_REP_SPD;
368 }
369
370 immr->im_ioport.iop_pcdat |= PC_REP_RES;
371 }
372 }
Simon Glass5dc88712012-01-14 15:24:47 +0000373 SHOW_BOOT_PROGRESS(BOOTSTAGE_ID_CHECK_MAGIC);
wdenk16f21702002-08-26 21:58:50 +0000374
375 return ((revision << 16) | (speed & 0xFFFF));
376}
377
378/* ------------------------------------------------------------------------- */
379
380#define SCC_SM 1 /* Index => SCC2 */
381#define PROFF PROFF_SCC2
382
383#define SMI_MSGLEN 8 /* Length of SMI Messages */
384
385#define PHYGPCR_ADDR 0x109 /* Port Enable */
386#define PHYPCR_ADDR 0x132 /* PHY Port Control Reg. (port 1) */
387#define LEDPCR_ADDR 0x141 /* LED Port Control Reg. */
388#define RPRESET_ADDR 0x144 /* Repeater Reset */
389
390#define PHYPCR_SPEED 0x2000 /* on for 100 Mbps, off for 10 Mbps */
391#define PHYPCR_AN 0x1000 /* on to enable Auto-Negotiation */
392#define PHYPCR_REST_AN 0x0200 /* on to restart Auto-Negotiation */
393#define PHYPCR_FDX 0x0100 /* on for Full Duplex, off for HDX */
394#define PHYPCR_COLT 0x0080 /* on to enable COL signal test */
395
396/* ------------------------------------------------------------------------- */
397
398/*
399 * Must run from RAM:
400 * uses parameter RAM area which is used for stack while running from ROM
401 */
402void hermes_start_lxt980 (int speed)
403{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200404 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
wdenk16f21702002-08-26 21:58:50 +0000405 volatile cpm8xx_t *cp = (cpm8xx_t *) & (immr->im_cpm);
406 volatile scc_t *sp = (scc_t *) & (cp->cp_scc[SCC_SM]);
407 volatile cbd_t *bd;
408 volatile hdlc_pram_t *hp;
409 uchar smimsg[SMI_MSGLEN];
410 ushort phypcrval;
411 uint bd_off;
412 int pnr;
413
414 printf ("LXT9880: %3d Mbps\n", speed);
415
416 immr->im_ioport.iop_paodr |= 0x0008; /* init PAODR: PA12 (TXD2) open drain */
417 immr->im_ioport.iop_papar |= 0x400c; /* init PAPAR: TXD2, RXD2, BRGO4 */
418 immr->im_ioport.iop_padir &= 0xbff3; /* init PADIR: BRGO4 */
419 immr->im_ioport.iop_padir |= 0x4000;
420
421 /* get temporary BD; no need for permanent alloc */
422 bd_off = dpram_base_align (8);
423
424 bd = (cbd_t *) (immr->im_cpm.cp_dpmem + bd_off);
425
426 bd->cbd_bufaddr = 0;
427 bd->cbd_datlen = 0;
428 bd->cbd_sc = BD_SC_WRAP | BD_SC_LAST | BD_SC_INTRPT | BD_SC_TC;
429
430 /* init. baudrate generator BRG4 */
431 cp->cp_brgc4 = (0x00010000 | (50 << 1)); /* output 1 MHz */
432
433 cp->cp_sicr &= 0xFFFF00FF; /* SICR: mask SCC2 */
434 cp->cp_sicr |= 0x00001B00; /* SICR: SCC2 clk BRG4 */
435
436 /* init SCC_SM register */
437 sp->scc_psmr = 0x0000; /* init PSMR: no additional flags */
438 sp->scc_todr = 0x0000;
439 sp->scc_dsr = 0x7e7e;
440
441 /* init. SCC_SM parameter area */
442 hp = (hdlc_pram_t *) & cp->cp_dparam[PROFF];
443
444 hp->tbase = bd_off; /* offset from beginning of DPRAM */
445
446 hp->rfcr = 0x18;
447 hp->tfcr = 0x18;
448 hp->mrblr = 10;
449
450 hp->c_mask = 0x0000f0b8;
451 hp->c_pres = 0x0000ffff;
452
453 hp->disfc = 0;
454 hp->crcec = 0;
455 hp->abtsc = 0;
456 hp->nmarc = 0;
457 hp->retrc = 0;
458
459 hp->mflr = 10;
460
461 hp->rfthr = 1;
462
463 hp->hmask = 0;
464 hp->haddr1 = 0;
465 hp->haddr2 = 0;
466 hp->haddr3 = 0;
467 hp->haddr4 = 0;
468
469 cp->cp_cpcr = SCC_SM << 6 | 0x0001; /* SCC_SM: init TX/RX params */
470 while (cp->cp_cpcr & CPM_CR_FLG);
471
472 /* clear all outstanding SCC events */
473 sp->scc_scce = ~0;
474
475 /* enable transmitter: GSMR_L: TPL=2(16bits), TPP=3(all ones), ENT */
476 sp->scc_gsmrh = 0;
477 sp->scc_gsmrl |= SCC_GSMRL_TPL_16 | SCC_GSMRL_TPP_ALL1 |
478 SCC_GSMRL_ENT | SCC_GSMRL_MODE_HDLC;
479
480#if 0
481 smimsg[0] = 0x00; /* CHIP/HUB ID */
482 smimsg[1] = 0x38; /* WRITE CMD */
483 smimsg[2] = (RPRESET_ADDR << 4) & 0xf0;
484 smimsg[3] = RPRESET_ADDR >> 4;
485 smimsg[4] = 0x01;
486 smimsg[5] = 0x00;
487 smimsg[6] = 0x00;
488 smimsg[7] = 0x00;
489
490 send_smi_frame (sp, bd, smimsg);
491#endif
492
493 smimsg[0] = 0x7f; /* BROADCAST */
494 smimsg[1] = 0x34; /* ASSIGN HUB ID */
495 smimsg[2] = 0x00;
496 smimsg[3] = 0x00;
497 smimsg[4] = 0x00; /* HUB ID = 0 */
498 smimsg[5] = 0x00;
499 smimsg[6] = 0x00;
500 smimsg[7] = 0x00;
501
502 send_smi_frame (sp, bd, smimsg);
503
504 smimsg[0] = 0x7f; /* BROADCAST */
505 smimsg[1] = 0x3c; /* SET ARBOUT TO 0 */
506 smimsg[2] = 0x00; /* ADDRESS = 0 */
507 smimsg[3] = 0x00;
508 smimsg[4] = 0x00; /* DATA = 0 */
509 smimsg[5] = 0x00;
510 smimsg[6] = 0x00;
511 smimsg[7] = 0x00;
512
513 send_smi_frame (sp, bd, smimsg);
514
515 if (speed == 100) {
516 phypcrval = PHYPCR_SPEED; /* 100 MBIT, disable autoneg. */
517 } else {
518 phypcrval = 0; /* 10 MBIT, disable autoneg. */
519 }
520
521 /* send MSGs */
522 for (pnr = 0; pnr < 8; pnr++) {
523 smimsg[0] = 0x00; /* CHIP/HUB ID */
524 smimsg[1] = 0x38; /* WRITE CMD */
525 smimsg[2] = ((PHYPCR_ADDR + pnr) << 4) & 0xf0;
526 smimsg[3] = (PHYPCR_ADDR + pnr) >> 4;
527 smimsg[4] = (unsigned char) (phypcrval & 0xff);
528 smimsg[5] = (unsigned char) (phypcrval >> 8);
529 smimsg[6] = 0x00;
530 smimsg[7] = 0x00;
531
532 send_smi_frame (sp, bd, smimsg);
533 }
534
535 smimsg[0] = 0x00; /* CHIP/HUB ID */
536 smimsg[1] = 0x38; /* WRITE CMD */
537 smimsg[2] = (PHYGPCR_ADDR << 4) & 0xf0;
538 smimsg[3] = PHYGPCR_ADDR >> 4;
539 smimsg[4] = 0xff; /* enable port 1-8 */
540 smimsg[5] = 0x01; /* enable MII1 (0x01) */
541 smimsg[6] = 0x00;
542 smimsg[7] = 0x00;
543
544 send_smi_frame (sp, bd, smimsg);
545
546 smimsg[0] = 0x00; /* CHIP/HUB ID */
547 smimsg[1] = 0x38; /* WRITE CMD */
548 smimsg[2] = (LEDPCR_ADDR << 4) & 0xf0;
549 smimsg[3] = LEDPCR_ADDR >> 4;
550 smimsg[4] = 0xaa; /* Port 1-8 Conf.bits = 10 (Hardware control) */
551 smimsg[5] = 0xaa;
552 smimsg[6] = 0x00;
553 smimsg[7] = 0x00;
554
555 send_smi_frame (sp, bd, smimsg);
556
557 /*
558 * Disable Transmitter (so that we can free the BD, too)
559 */
560 sp->scc_gsmrl &= ~SCC_GSMRL_ENT;
561}
562
563/* ------------------------------------------------------------------------- */
564
565static void send_smi_frame (volatile scc_t * sp, volatile cbd_t * bd,
566 uchar * msg)
567{
568#ifdef DEBUG
569 unsigned hub, chip, cmd, length, addr;
570
571 hub = msg[0] & 0x1F;
572 chip = msg[0] >> 5;
573 cmd = msg[1] & 0x1F;
574 length = (msg[1] >> 5) | ((msg[2] & 0x0F) << 3);
575 addr = (msg[2] >> 4) | (msg[3] << 4);
576
577 printf ("SMI send: Hub %02x Chip %x Cmd %02x Len %d Addr %03x: "
578 "%02x %02x %02x %02x\n",
579 hub, chip, cmd, length, addr, msg[4], msg[5], msg[6], msg[7]);
580#endif /* DEBUG */
581
582 bd->cbd_bufaddr = (uint) msg;
583 bd->cbd_datlen = SMI_MSGLEN;
584 bd->cbd_sc |= BD_SC_READY;
585
586 /* wait for msg transmitted */
587 while ((sp->scc_scce & 0x0002) == 0);
588 /* clear all events */
589 sp->scc_scce = ~0;
590}
591
592/* ------------------------------------------------------------------------- */
593
594void show_boot_progress (int status)
595{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200596 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
wdenk16f21702002-08-26 21:58:50 +0000597
Simon Glass8ade9502011-12-10 11:07:58 +0000598 /* let things compatible */
599 if (status < -BOOTSTAGE_ID_POST_FAIL_R)
600 status = -1;
wdenk16f21702002-08-26 21:58:50 +0000601 status ^= 0x0F;
602 status = (status & 0x0F) << 14;
603 immr->im_cpm.cp_pbdat = (immr->im_cpm.cp_pbdat & ~PB_LED_ALL) | status;
604}
605
606/* ------------------------------------------------------------------------- */