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Wolfgang Denkf901a832005-08-06 01:42:58 +02001/*
2 * Copyright (C) 2004 Arabella Software Ltd.
3 * Yuli Barcohen <yuli@arabellasw.com>
4 *
5 * U-Boot configuration for Embedded Planet EP8248 boards.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29#define CONFIG_MPC8248
30#define CPU_ID_STR "MPC8248"
31
32#define CONFIG_EP8248 /* Embedded Planet EP8248 board */
33
Wolfgang Denkf901a832005-08-06 01:42:58 +020034#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
35
36/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
37#define CONFIG_ENV_OVERWRITE
38
39/*
40 * Select serial console configuration
41 *
42 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
43 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
44 * for SCC).
45 */
46#define CONFIG_CONS_ON_SMC /* Console is on SMC */
47#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
48#undef CONFIG_CONS_NONE /* It's not on external UART */
49#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
50
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020051#define CONFIG_SYS_BCSR 0xFA000000
Wolfgang Denkf901a832005-08-06 01:42:58 +020052
Marcel Ziswiler45f89f32009-09-09 21:22:08 +020053/* Pass open firmware flat device tree */
54#define CONFIG_OF_LIBFDT 1
55#define CONFIG_OF_BOARD_SETUP 1
56
57#define OF_TBCLK (bd->bi_busfreq / 4)
58#define OF_STDOUT_PATH "/soc/cpm/serial <at> 11a80"
59
60/* Select ethernet configuration */
Wolfgang Denkf901a832005-08-06 01:42:58 +020061#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
62#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
63#undef CONFIG_ETHER_NONE /* No external Ethernet */
64
Marcel Ziswiler45f89f32009-09-09 21:22:08 +020065#define CONFIG_NET_MULTI
66#define CONFIG_SYS_CPMFCR_RAMTYPE 0
67#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
Wolfgang Denkf901a832005-08-06 01:42:58 +020068
Marcel Ziswiler45f89f32009-09-09 21:22:08 +020069#define CONFIG_HAS_ETH0
70#define CONFIG_ETHER_ON_FCC1 1
Wolfgang Denkf901a832005-08-06 01:42:58 +020071/* - Rx clock is CLK10
72 * - Tx clock is CLK11
73 * - BDs/buffers on 60x bus
74 * - Full duplex
75 */
Marcel Ziswiler45f89f32009-09-09 21:22:08 +020076#define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
77#define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK10 | CMXFCR_TF1CS_CLK11)
Wolfgang Denkf901a832005-08-06 01:42:58 +020078
Marcel Ziswiler45f89f32009-09-09 21:22:08 +020079#define CONFIG_HAS_ETH1
80#define CONFIG_ETHER_ON_FCC2 1
Wolfgang Denkf901a832005-08-06 01:42:58 +020081/* - Rx clock is CLK13
82 * - Tx clock is CLK14
83 * - BDs/buffers on 60x bus
84 * - Full duplex
85 */
Marcel Ziswiler45f89f32009-09-09 21:22:08 +020086#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
87#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
Wolfgang Denkf901a832005-08-06 01:42:58 +020088
89#define CONFIG_MII /* MII PHY management */
90#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
91/*
92 * GPIO pins used for bit-banged MII communications
93 */
94#define MDIO_PORT 0 /* Not used - implemented in BCSR */
Luigi 'Comio' Mantellinibe225442009-10-10 12:42:22 +020095
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define MDIO_ACTIVE (*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFB)
97#define MDIO_TRISTATE (*(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x04)
98#define MDIO_READ (*(vu_char *)(CONFIG_SYS_BCSR + 8) & 1)
Wolfgang Denkf901a832005-08-06 01:42:58 +020099
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#define MDIO(bit) if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x01; \
101 else *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFE
Wolfgang Denkf901a832005-08-06 01:42:58 +0200102
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define MDC(bit) if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x02; \
104 else *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFD
Wolfgang Denkf901a832005-08-06 01:42:58 +0200105
106#define MIIDELAY udelay(1)
107
Wolfgang Denkf901a832005-08-06 01:42:58 +0200108#ifndef CONFIG_8260_CLKIN
109#define CONFIG_8260_CLKIN 66000000 /* in Hz */
110#endif
111
112#define CONFIG_BAUDRATE 38400
113
Wolfgang Denkf901a832005-08-06 01:42:58 +0200114
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500115/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -0500116 * BOOTP options
117 */
118#define CONFIG_BOOTP_BOOTFILESIZE
119#define CONFIG_BOOTP_BOOTPATH
120#define CONFIG_BOOTP_GATEWAY
121#define CONFIG_BOOTP_HOSTNAME
122
123
124/*
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500125 * Command line configuration.
126 */
127#include <config_cmd_default.h>
128
129#define CONFIG_CMD_DHCP
130#define CONFIG_CMD_ECHO
131#define CONFIG_CMD_I2C
132#define CONFIG_CMD_IMMAP
133#define CONFIG_CMD_MII
134#define CONFIG_CMD_PING
135
Wolfgang Denkf901a832005-08-06 01:42:58 +0200136
137#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
138#define CONFIG_BOOTCOMMAND "bootm FF860000" /* autoboot command */
139#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=phys:7M(root),-(root)ro"
140
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500141#if defined(CONFIG_CMD_KGDB)
Wolfgang Denkf901a832005-08-06 01:42:58 +0200142#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
143#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
144#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
145#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */
146#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
147#endif
148
149#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
150#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
151
152/*
153 * Miscellaneous configurable options
154 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_HUSH_PARSER
156#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
157#define CONFIG_SYS_LONGHELP /* undef to save memory */
158#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500159#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200161#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200163#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
165#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
166#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200167
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
169#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200170
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200172
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200174
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
Wolfgang Denkf901a832005-08-06 01:42:58 +0200176
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_FLASH_BASE 0xFF800000
178#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200179#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
181#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200182
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_DIRECT_FLASH_TFTP
Wolfgang Denkf901a832005-08-06 01:42:58 +0200184
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500185#if defined(CONFIG_CMD_JFFS2)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_JFFS2_FIRST_BANK 0
187#define CONFIG_SYS_JFFS2_NUM_BANKS CONFIG_SYS_MAX_FLASH_BANKS
188#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0
189#define CONFIG_SYS_JFFS2_LAST_SECTOR 62
190#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
191#define CONFIG_SYS_JFFS_CUSTOM_PART
Jon Loeliger80ff4f92007-07-10 09:29:01 -0500192#endif
Wolfgang Denkf901a832005-08-06 01:42:58 +0200193
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500194#if defined(CONFIG_CMD_I2C)
Wolfgang Denkf901a832005-08-06 01:42:58 +0200195#define CONFIG_HARD_I2C 1 /* To enable I2C support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */
197#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
Jon Loeliger80ff4f92007-07-10 09:29:01 -0500198#endif
Wolfgang Denkf901a832005-08-06 01:42:58 +0200199
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
201#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
202#define CONFIG_SYS_RAMBOOT
Wolfgang Denkf901a832005-08-06 01:42:58 +0200203#endif
204
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200206
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200207#define CONFIG_ENV_IS_IN_FLASH
Wolfgang Denkf901a832005-08-06 01:42:58 +0200208
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200209#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200210#define CONFIG_ENV_SECT_SIZE 0x20000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200212#endif /* CONFIG_ENV_IS_IN_FLASH */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200213
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_DEFAULT_IMMR 0x00010000
Wolfgang Denkf901a832005-08-06 01:42:58 +0200215
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_IMMR 0xF0000000
Wolfgang Denkf901a832005-08-06 01:42:58 +0200217
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
219#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
220#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
221#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
222#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Wolfgang Denkf901a832005-08-06 01:42:58 +0200223
224/* Hard reset configuration word */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_HRCW_MASTER 0x0C40025A /* Not used - provided by FPGA */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200226/* No slaves */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_HRCW_SLAVE1 0
228#define CONFIG_SYS_HRCW_SLAVE2 0
229#define CONFIG_SYS_HRCW_SLAVE3 0
230#define CONFIG_SYS_HRCW_SLAVE4 0
231#define CONFIG_SYS_HRCW_SLAVE5 0
232#define CONFIG_SYS_HRCW_SLAVE6 0
233#define CONFIG_SYS_HRCW_SLAVE7 0
Wolfgang Denkf901a832005-08-06 01:42:58 +0200234
235#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
236#define BOOTFLAG_WARM 0x02 /* Software reboot */
237
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
239#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200240
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
Jon Loeliger1bec3d32007-07-04 22:32:10 -0500242#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Wolfgang Denkf901a832005-08-06 01:42:58 +0200244#endif
245
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_HID0_INIT 0
247#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
Wolfgang Denkf901a832005-08-06 01:42:58 +0200248
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_HID2 0
Wolfgang Denkf901a832005-08-06 01:42:58 +0200250
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_SIUMCR 0x01240200
252#define CONFIG_SYS_SYPCR 0xFFFF0683
253#define CONFIG_SYS_BCR 0x00000000
254#define CONFIG_SYS_SCCR SCCR_DFBRG01
Wolfgang Denkf901a832005-08-06 01:42:58 +0200255
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_RMR RMR_CSRE
257#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
258#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
259#define CONFIG_SYS_RCCR 0
Wolfgang Denkf901a832005-08-06 01:42:58 +0200260
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_MPTPR 0x1300
262#define CONFIG_SYS_PSDMR 0x82672522
263#define CONFIG_SYS_PSRT 0x4B
Wolfgang Denkf901a832005-08-06 01:42:58 +0200264
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_SDRAM_BASE 0x00000000
266#define CONFIG_SYS_SDRAM_BR (CONFIG_SYS_SDRAM_BASE | 0x00001841)
267#define CONFIG_SYS_SDRAM_OR 0xFF0030C0
Wolfgang Denkf901a832005-08-06 01:42:58 +0200268
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001801)
270#define CONFIG_SYS_OR0_PRELIM 0xFF8008C2
271#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_BCSR | 0x00000801)
272#define CONFIG_SYS_OR2_PRELIM 0xFFF00864
Wolfgang Denkf901a832005-08-06 01:42:58 +0200273
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_RESET_ADDRESS 0xC0000000
Wolfgang Denkf901a832005-08-06 01:42:58 +0200275
276#endif /* __CONFIG_H */