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gaurav ranaa2e225e2015-02-27 09:43:49 +05301/*
2 * Copyright 2015 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef _FSL_SFP_SNVS_
8#define _FSL_SFP_SNVS_
9
10#include <common.h>
11#include <config.h>
12#include <asm/io.h>
13
14#ifdef CONFIG_SYS_FSL_SRK_LE
15#define srk_in32(a) in_le32(a)
16#else
17#define srk_in32(a) in_be32(a)
18#endif
19
20#ifdef CONFIG_SYS_FSL_SFP_LE
21#define sfp_in32(a) in_le32(a)
22#define sfp_out32(a, v) out_le32(a, v)
23#define sfp_in16(a) in_le16(a)
24#elif defined(CONFIG_SYS_FSL_SFP_BE)
25#define sfp_in32(a) in_be32(a)
26#define sfp_out32(a, v) out_be32(a, v)
27#define sfp_in16(a) in_be16(a)
28#else
29#error Neither CONFIG_SYS_FSL_SFP_LE nor CONFIG_SYS_FSL_SFP_BE is defined
30#endif
31
32/* Number of SRKH registers */
33#define NUM_SRKH_REGS 8
34
Saksham Jain38081902016-03-23 16:24:32 +053035#if defined(CONFIG_SYS_FSL_SFP_VER_3_2) || \
36 defined(CONFIG_SYS_FSL_SFP_VER_3_4)
gaurav ranaa2e225e2015-02-27 09:43:49 +053037struct ccsr_sfp_regs {
38 u32 ospr; /* 0x200 */
39 u32 ospr1; /* 0x204 */
40 u32 reserved1[4];
41 u32 fswpr; /* 0x218 FSL Section Write Protect */
42 u32 fsl_uid; /* 0x21c FSL UID 0 */
43 u32 fsl_uid_1; /* 0x220 FSL UID 0 */
44 u32 reserved2[12];
45 u32 srk_hash[8]; /* 0x254 Super Root Key Hash */
46 u32 oem_uid; /* 0x274 OEM UID 0*/
47 u32 oem_uid_1; /* 0x278 OEM UID 1*/
48 u32 oem_uid_2; /* 0x27c OEM UID 2*/
49 u32 oem_uid_3; /* 0x280 OEM UID 3*/
50 u32 oem_uid_4; /* 0x284 OEM UID 4*/
51 u32 reserved3[8];
52};
53#elif defined(CONFIG_SYS_FSL_SFP_VER_3_0)
54struct ccsr_sfp_regs {
55 u32 ospr; /* 0x200 */
56 u32 reserved0[14];
57 u32 srk_hash[NUM_SRKH_REGS]; /* 0x23c Super Root Key Hash */
58 u32 oem_uid; /* 0x9c OEM Unique ID */
59 u8 reserved2[0x04];
60 u32 ovpr; /* 0xA4 Intent To Secure */
61 u8 reserved4[0x08];
62 u32 fsl_uid; /* 0xB0 FSL Unique ID */
63 u8 reserved5[0x04];
64 u32 fsl_spfr0; /* Scratch Pad Fuse Register 0 */
65 u32 fsl_spfr1; /* Scratch Pad Fuse Register 1 */
66
67};
68#else
69struct ccsr_sfp_regs {
70 u8 reserved0[0x40];
71 u32 ospr; /* 0x40 OEM Security Policy Register */
72 u8 reserved2[0x38];
73 u32 srk_hash[8]; /* 0x7c Super Root Key Hash */
74 u32 oem_uid; /* 0x9c OEM Unique ID */
75 u8 reserved4[0x4];
76 u32 ovpr; /* 0xA4 OEM Validation Policy Register */
77 u8 reserved8[0x8];
78 u32 fsl_uid; /* 0xB0 FSL Unique ID */
79};
80#endif
Sumit Gargabd9c1b2016-09-07 12:17:34 -040081
gaurav ranaa2e225e2015-02-27 09:43:49 +053082#define ITS_MASK 0x00000004
83#define ITS_BIT 2
Sumit Gargabd9c1b2016-09-07 12:17:34 -040084
85#if defined(CONFIG_SYS_FSL_SFP_VER_3_4)
86#define OSPR_KEY_REVOC_SHIFT 9
87#define OSPR_KEY_REVOC_MASK 0x0000fe00
88#else
89#define OSPR_KEY_REVOC_SHIFT 13
90#define OSPR_KEY_REVOC_MASK 0x0000e000
91#endif /* CONFIG_SYS_FSL_SFP_VER_3_4 */
gaurav ranaa2e225e2015-02-27 09:43:49 +053092
93#endif