blob: ce2c3e29dd17280c8ae74feed621d064d4880065 [file] [log] [blame]
Heiko Schocher67fa8c22010-02-22 16:43:02 +05301#
2# (C) Copyright 2010
3# Heiko Schocher, DENX Software Engineering, hs@denx.de.
4#
Wolfgang Denk1a459662013-07-08 09:37:19 +02005# SPDX-License-Identifier: GPL-2.0+
Heiko Schocher67fa8c22010-02-22 16:43:02 +05306#
Anatolij Gustschinb1e6c4c2013-04-30 11:15:33 +00007# Refer doc/README.kwbimage for more details about how-to configure
Heiko Schocher67fa8c22010-02-22 16:43:02 +05308# and create kirkwood boot image
9#
10
11# Boot Media configurations
12BOOT_FROM spi # Boot from SPI flash
13
Heiko Schocher1ebbb772011-02-22 09:34:33 +010014DATA 0xFFD10000 0x01112222 # MPP Control 0 Register
15# bit 3-0: MPPSel0 2, NF_IO[2]
16# bit 7-4: MPPSel1 2, NF_IO[3]
17# bit 12-8: MPPSel2 2, NF_IO[4]
18# bit 15-12: MPPSel3 2, NF_IO[5]
Heiko Schocher67fa8c22010-02-22 16:43:02 +053019# bit 19-16: MPPSel4 1, NF_IO[6]
20# bit 23-20: MPPSel5 1, NF_IO[7]
21# bit 27-24: MPPSel6 1, SYSRST_O
22# bit 31-28: MPPSel7 0, GPO[7]
23
Heiko Schocher1ebbb772011-02-22 09:34:33 +010024DATA 0xFFD10004 0x03303300
25
Heiko Schocher67fa8c22010-02-22 16:43:02 +053026DATA 0xFFD10008 0x00001100 # MPP Control 2 Register
27# bit 3-0: MPPSel16 0, GPIO[16]
28# bit 7-4: MPPSel17 0, GPIO[17]
29# bit 12-8: MPPSel18 1, NF_IO[0]
30# bit 15-12: MPPSel19 1, NF_IO[1]
31# bit 19-16: MPPSel20 0, GPIO[20]
32# bit 23-20: MPPSel21 0, GPIO[21]
33# bit 27-24: MPPSel22 0, GPIO[22]
34# bit 31-28: MPPSel23 0, GPIO[23]
35
36DATA 0xFFD100E0 0x1B1B1B1B # IO Configuration 0 Register
Heiko Schocher1ebbb772011-02-22 09:34:33 +010037DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
38DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
Holger Brunck24722162012-11-02 00:15:07 +000039
40# NOTE: Don't write on 0x20148 , 0x2014c and 0x20154, leave them untouched!
41# If not it could cause KW Exceptions during boot in Fast Corners/High Voltage
Heiko Schocher67fa8c22010-02-22 16:43:02 +053042
43#Dram initalization
44DATA 0xFFD01400 0x43000400 # SDRAM Configuration Register
45# bit13-0: 0x400 (DDR2 clks refresh rate)
46# bit23-14: zero
47# bit24: 1= enable exit self refresh mode on DDR access
48# bit25: 1 required
49# bit29-26: zero
50# bit31-30: 01
51
Heiko Schocher1ebbb772011-02-22 09:34:33 +010052DATA 0xFFD01404 0x39543000 # DDR Controller Control Low
Heiko Schocher67fa8c22010-02-22 16:43:02 +053053# bit 3-0: 0 reserved
54# bit 4: 0=addr/cmd in smame cycle
55# bit 5: 0=clk is driven during self refresh, we don't care for APX
56# bit 6: 0=use recommended falling edge of clk for addr/cmd
57# bit14: 0=input buffer always powered up
58# bit18: 1=cpu lock transaction enabled
59# bit23-20: 3=recommended value for CL=3 and STARTBURST_DEL disabled bit31=0
60# bit27-24: 6= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
61# bit30-28: 3 required
62# bit31: 0=no additional STARTBURST delay
63
Heiko Schocher1ebbb772011-02-22 09:34:33 +010064DATA 0xFFD01408 0x34136552 # DDR Timing (Low) (active cycles value +1)
Heiko Schocher67fa8c22010-02-22 16:43:02 +053065# bit3-0: TRAS lsbs
66# bit7-4: TRCD
67# bit11- 8: TRP
68# bit15-12: TWR
69# bit19-16: TWTR
70# bit20: TRAS msb
71# bit23-21: 0x0
72# bit27-24: TRRD
73# bit31-28: TRTP
74
Heiko Schocher1ebbb772011-02-22 09:34:33 +010075DATA 0xFFD0140C 0x00000033 # DDR Timing (High)
Heiko Schocher67fa8c22010-02-22 16:43:02 +053076# bit6-0: TRFC
77# bit8-7: TR2R
78# bit10-9: TR2W
79# bit12-11: TW2W
80# bit31-13: zero required
81
82DATA 0xFFD01410 0x0000000D # DDR Address Control
83# bit1-0: 01, Cs0width=x16
84# bit3-2: 11, Cs0size=1Gb
85# bit5-4: 00, Cs2width=nonexistent
86# bit7-6: 00, Cs1size =nonexistent
87# bit9-8: 00, Cs2width=nonexistent
88# bit11-10: 00, Cs2size =nonexistent
89# bit13-12: 00, Cs3width=nonexistent
90# bit15-14: 00, Cs3size =nonexistent
91# bit16: 0, Cs0AddrSel
92# bit17: 0, Cs1AddrSel
93# bit18: 0, Cs2AddrSel
94# bit19: 0, Cs3AddrSel
95# bit31-20: 0 required
96
97DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
98# bit0: 0, OpenPage enabled
99# bit31-1: 0 required
100
101DATA 0xFFD01418 0x00000000 # DDR Operation
102# bit3-0: 0x0, DDR cmd
103# bit31-4: 0 required
104
Heiko Schocher1ebbb772011-02-22 09:34:33 +0100105DATA 0xFFD0141C 0x00000652 # DDR Mode
106DATA 0xFFD01420 0x00000044 # DDR Extended Mode
Heiko Schocher67fa8c22010-02-22 16:43:02 +0530107# bit0: 0, DDR DLL enabled
108# bit1: 0, DDR drive strenght normal
109# bit2: 1, DDR ODT control lsd disabled
110# bit5-3: 000, required
111# bit6: 1, DDR ODT control msb, enabled
112# bit9-7: 000, required
113# bit10: 0, differential DQS enabled
114# bit11: 0, required
115# bit12: 0, DDR output buffer enabled
116# bit31-13: 0 required
117
118DATA 0xFFD01424 0x0000F07F # DDR Controller Control High
119# bit2-0: 111, required
120# bit3 : 1 , MBUS Burst Chop disabled
121# bit6-4: 111, required
122# bit7 : 0
123# bit8 : 0 , no sample stage
124# bit9 : 0 , no half clock cycle addition to dataout
125# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
126# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
127# bit15-12: 1111 required
128# bit31-16: 0 required
Heiko Schocher1ebbb772011-02-22 09:34:33 +0100129DATA 0xFFD01428 0x00074510
130DATA 0xFFD0147c 0x00007451
Heiko Schocher67fa8c22010-02-22 16:43:02 +0530131
132DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
133DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
134# bit0: 1, Window enabled
135# bit1: 0, Write Protect disabled
136# bit3-2: 00, CS0 hit selected
137# bit23-4: ones, required
138# bit31-24: 0x07, Size (i.e. 128MB)
139
140DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
141DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
142DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
143
Heiko Schocher1ebbb772011-02-22 09:34:33 +0100144DATA 0xFFD01494 0x00010001 # DDR ODT Control (Low)
Heiko Schocher67fa8c22010-02-22 16:43:02 +0530145# bit3-0: 0, ODT0Rd, MODT[0] asserted during read from DRAM CS0
146# bit19-16:0, ODT0Wr, MODT[0] asserted during write to DRAM CS0
147
148DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
149# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
150# bit3-2: 00, ODT1 controlled by register
151# bit31-4: zero, required
152
Heiko Schocher1ebbb772011-02-22 09:34:33 +0100153DATA 0xFFD0149C 0x0000FC11 # CPU ODT Control
Heiko Schocher67fa8c22010-02-22 16:43:02 +0530154# bit3-0: F, ODT0Rd, Internal ODT asserted during read from DRAM bank0
155# bit7-4: 0, ODT0Wr, Internal ODT asserted during write to DRAM bank0
156# bit9-8: 1, ODTEn, never active
157# bit11-10:2, DQ_ODTSel. ODT select turned on, 75 ohm
158
159DATA 0xFFD01480 0x00000001 # DDR Initialization Control
Prafulla Wadaskar637833c2010-03-03 15:27:37 +0530160# bit0=1, enable DDR init upon this register write
Heiko Schocher67fa8c22010-02-22 16:43:02 +0530161
162# End of Header extension
163DATA 0x0 0x0