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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 400558b561e2bdb47f87b96b3510dda0881a3662 / . / include / configs / xm250.h
blob: 1be7dd46a7df35a5b219f33d7d3338b438f654e9 [file] [log] [blame]
wdenkefa329c2004-03-23 20:18:25 +0000[diff] [blame]1/*
2 * (C) Copyright 2002
3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4 *
5 * (C) Copyright 2002
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * If we are developing, we might want to start armboot from ram
33 * so we MUST NOT initialize critical regs like mem-timing ...
34 */
wdenk400558b2005-04-02 23:52:25 +0000[diff] [blame^]35#define CONFIG_INIT_CRITICAL
wdenkefa329c2004-03-23 20:18:25 +0000[diff] [blame]36
37/*
38 * High Level Configuration Options
39 * (easy to change)
40 */
41#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
42#define CONFIG_XM250 1 /* on a MicroSys XM250 Board */
43#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
44
45/*
46 * Size of malloc() pool; this lives below the uppermost 128 KiB which are
47 * used for the RAM copy of the uboot code
48 *
49 */
50#define CFG_MALLOC_LEN (256*1024)
51#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
52
53/*
54 * Hardware drivers
55 */
56#define CONFIG_DRIVER_SMC91111
57#define CONFIG_SMC91111_BASE 0x04000300
58#undef CONFIG_SMC91111_EXT_PHY
59#define CONFIG_SMC_USE_32_BIT
60#undef CONFIG_SHOW_ACTIVITY
61#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
62
63/*
64 * I2C bus
65 */
66#define CONFIG_HARD_I2C 1
67#define CFG_I2C_SPEED 50000
68#define CFG_I2C_SLAVE 0xfe
69
70#define CONFIG_RTC_PCF8563 1
71#define CFG_I2C_RTC_ADDR 0x51
72
73#define CFG_I2C_EEPROM_ADDR 0x58 /* A0 = 0 (hardwired) */
74#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* 4 bits = 16 octets */
75#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* between stop and start */
76#define CFG_I2C_EEPROM_ADDR_LEN 1 /* length of address */
77#define CFG_EEPROM_SIZE 2048 /* size in bytes */
78#undef CFG_I2C_INIT_BOARD /* board has no own init */
79
80/*
81 * select serial console configuration
82 */
83#define CONFIG_FFUART 1 /* we use FFUART */
84
85/* allow to overwrite serial and ethaddr */
86#define CONFIG_ENV_OVERWRITE
87
88#define CONFIG_BAUDRATE 115200
89
90#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
91 CFG_CMD_ELF | \
92 CFG_CMD_EEPROM | \
93 CFG_CMD_DATE | \
94 CFG_CMD_I2C )
95
96/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
97#include <cmd_confdefs.h>
98
99#define CONFIG_BOOTDELAY 3
100
101/*
102 * Miscellaneous configurable options
103 */
104#define CFG_LONGHELP /* undef to save memory */
105#define CFG_PROMPT "=> " /* Monitor Command Prompt */
106#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
107#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
108#define CFG_MAXARGS 16 /* max number of command args */
109#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
110
111#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */
112#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
113
114#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
115
116#define CFG_LOAD_ADDR 0xa3000000 /* default load address */
117
118#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
119#define CFG_CPUSPEED 0x161 /* set core clock to 400/400/100 MHz */
120
121 /* valid baudrates */
122
123#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
124
125/*
126 * Definitions related to passing arguments to kernel.
127 */
128#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */
129#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */
130#undef CONFIG_INITRD_TAG /* do not send initrd params */
131#undef CONFIG_VFD /* do not send framebuffer setup */
132
133/*
134 * Stack sizes
135 *
136 * The stack sizes are set up in start.S using the settings below
137 */
138#define CONFIG_STACKSIZE (128*1024) /* regular stack */
139#ifdef CONFIG_USE_IRQ
140#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
141#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
142#endif
143
144/*
145 * Physical Memory Map
146 */
147#define CONFIG_NR_DRAM_BANKS 4
148#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
149#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
150#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
151#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
152#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
153#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
154#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
155#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
156
157#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
158#define PHYS_FLASH_2 0x04000000 /* Flash Bank #1 */
159#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
160#define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */
161#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
162
163#define CFG_DRAM_BASE 0xa0000000
164#define CFG_DRAM_SIZE 0x04000000
165
166#define CFG_FLASH_BASE PHYS_FLASH_1
167
168/*
169 * FLASH and environment organization
170 */
171#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
172#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
173
174/* timeout values are in ticks */
175#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
176#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
177#define CFG_FLASH_LOCK_TOUT (2*CFG_HZ) /* Timeout for Flash Set Lock Bit */
178#define CFG_FLASH_UNLOCK_TOUT (2*CFG_HZ) /* Timeout for Flash Clear Lock Bits */
179#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
180
181#define CFG_ENV_IS_IN_FLASH 1
182#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) /* Addr of Environment Sector */
183#define CFG_ENV_SIZE 0x4000
184#define CFG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */
185#define CFG_MONITOR_LEN 0x20000 /* 128 KiB */
186
187/******************************************************************************
188 *
189 * CPU specific defines
190 *
191 ******************************************************************************/
192
193/*
194 * GPIO settings
195 *
196 * GPIO pin assignments
197 * GPIO Name Dir Out AF
198 * 0 NC
199 * 1 NC
200 * 2 SIRQ1 I
201 * 3 SIRQ2 I
202 * 4 SIRQ3 I
203 * 5 DMAACK1 O 0
204 * 6 DMAACK2 O 0
205 * 7 DMAACK3 O 0
206 * 8 TC1 O 0
207 * 9 TC2 O 0
208 * 10 TC3 O 0
209 * 11 nDMAEN O 1
210 * 12 AENCTRL O 0
211 * 13 PLDTC O 0
212 * 14 ETHIRQ I
213 * 15 NC
214 * 16 NC
215 * 17 NC
216 * 18 RDY I
217 * 19 DMASIO I
218 * 20 ETHIRQ NC
219 * 21 NC
220 * 22 PGMEN O 1 FIXME for debug only enable flash
221 * 23 NC
222 * 24 NC
223 * 25 NC
224 * 26 NC
225 * 27 NC
226 * 28 NC
227 * 29 NC
228 * 30 NC
229 * 31 NC
230 * 32 NC
231 * 33 NC
232 * 34 FFRXD I 01
233 * 35 FFCTS I 01
234 * 36 FFDCD I 01
235 * 37 FFDSR I 01
236 * 38 FFRI I 01
237 * 39 FFTXD O 1 10
238 * 40 FFDTR O 0 10
239 * 41 FFRTS O 0 10
240 * 42 RS232FOFF O 0 00
241 * 43 NC
242 * 44 NC
243 * 45 IRSL0 O 0
244 * 46 IRRX0 I 01
245 * 47 IRTX0 O 0 10
246 * 48 NC
247 * 49 nIOWE O 0
248 * 50 NC
249 * 51 NC
250 * 52 NC
251 * 53 NC
252 * 54 NC
253 * 55 NC
254 * 56 NC
255 * 57 NC
256 * 58 DKDIRQ I
257 * 59 NC
258 * 60 NC
259 * 61 NC
260 * 62 NC
261 * 63 NC
262 * 64 COMLED O 0
263 * 65 COMLED O 0
264 * 66 COMLED O 0
265 * 67 COMLED O 0
266 * 68 COMLED O 0
267 * 69 COMLED O 0
268 * 70 COMLED O 0
269 * 71 COMLED O 0
270 * 72 NC
271 * 73 NC
272 * 74 NC
273 * 75 NC
274 * 76 NC
275 * 77 NC
276 * 78 CSIO O 1
277 * 79 NC
278 * 80 CSETH O 1
279 *
280 * NOTE: All NC's are defined to be outputs
281 *
282 */
283/* Pin direction control */
284#define CFG_GPDR0_VAL 0xd3808000
285#define CFG_GPDR1_VAL 0xfcffab83
286#define CFG_GPDR2_VAL 0x0001ffff
287/* Set and Clear registers */
288#define CFG_GPSR0_VAL 0x00008000
289#define CFG_GPSR1_VAL 0x00ff0002
290#define CFG_GPSR2_VAL 0x0001c000
291#define CFG_GPCR0_VAL 0x00000000
292#define CFG_GPCR1_VAL 0x00000000
293#define CFG_GPCR2_VAL 0x00000000
294/* Edge detect registers (these are set by the kernel) */
295#define CFG_GRER0_VAL 0x00002180
296#define CFG_GRER1_VAL 0x00000000
297#define CFG_GRER2_VAL 0x00000000
298#define CFG_GFER0_VAL 0x000043e0
299#define CFG_GFER1_VAL 0x00000000
300#define CFG_GFER2_VAL 0x00000000
301/* Alternate function registers */
302#define CFG_GAFR0_L_VAL 0x80000004
303#define CFG_GAFR0_U_VAL 0x595a8010
304#define CFG_GAFR1_L_VAL 0x699a9559
305#define CFG_GAFR1_U_VAL 0xaaa5aaaa
306#define CFG_GAFR2_L_VAL 0xaaaaaaaa
307#define CFG_GAFR2_U_VAL 0x00000002
308
309/*
310 * Clocks, power control and interrupts
311 */
312#define CFG_PSSR_VAL 0x00000030
313#define CFG_CCCR_VAL 0x00000161 /* 100 MHz memory, 400 MHz CPU, 400 Turbo */
314#define CFG_CKEN_VAL 0x000141ec /* FFUART and STUART enabled */
315#define CFG_ICMR_VAL 0x00000000 /* No interrupts enabled */
316
317/* FIXME
318 *
319 * RTC settings
320 * Watchdog
321 *
322 */
323
324/*
325 * Memory settings
326 *
327 */
328#define CFG_MSC0_VAL 0x122423f0 /* FLASH / LAN (cs0)/(cS1) */
329#define CFG_MSC1_VAL 0x35f4aa4c /* USB / ST3+ST5 (cs2)/(cS3) */
330#define CFG_MSC2_VAL 0x35f435fc /* IDE / BCR + WatchDog (cs4)/(cS5) */
331#define CFG_MDCNFG_VAL 0x000009c9
332#define CFG_MDMRS_VAL 0x00220022
wdenk400558b2005-04-02 23:52:25 +0000[diff] [blame^]333#define CFG_MDREFR_VAL 0x000da018 /* Initial setting, individual bits set in lowlevel_init.S */
wdenkefa329c2004-03-23 20:18:25 +0000[diff] [blame]334
335/*
336 * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
337 */
338#define CFG_MECR_VAL 0x00000000
339#define CFG_MCMEM0_VAL 0x00010504
340#define CFG_MCMEM1_VAL 0x00010504
341#define CFG_MCATT0_VAL 0x00010504
342#define CFG_MCATT1_VAL 0x00010504
343#define CFG_MCIO0_VAL 0x00004715
344#define CFG_MCIO1_VAL 0x00004715
345
346/* Board specific defines */
347
348#ifndef __ASSEMBLY__
349
350/* global prototypes */
351void led_code(int code, int color);
352
353#endif
354
355#endif /* __CONFIG_H */