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Tor Krill9536dfc2008-03-15 15:40:26 +01001/*
2 * (C) Copyright 2008
3 * Tor Krill, Excito Elektronik i Skåne , tor@excito.com
4 *
5 * Modelled after the ds1337 driver
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * Date & Time support (no alarms) for Intersil
25 * ISL1208 Real Time Clock (RTC).
26 */
27
28#include <common.h>
29#include <command.h>
30#include <rtc.h>
31#include <i2c.h>
32
33/*---------------------------------------------------------------------*/
34#ifdef DEBUG_RTC
35#define DEBUGR(fmt,args...) printf(fmt ,##args)
36#else
37#define DEBUGR(fmt,args...)
38#endif
39/*---------------------------------------------------------------------*/
40
41/*
42 * RTC register addresses
43 */
44
45#define RTC_SEC_REG_ADDR 0x0
46#define RTC_MIN_REG_ADDR 0x1
47#define RTC_HR_REG_ADDR 0x2
48#define RTC_DATE_REG_ADDR 0x3
49#define RTC_MON_REG_ADDR 0x4
50#define RTC_YR_REG_ADDR 0x5
51#define RTC_DAY_REG_ADDR 0x6
52#define RTC_STAT_REG_ADDR 0x7
53/*
54 * RTC control register bits
55 */
56
57/*
58 * RTC status register bits
59 */
60#define RTC_STAT_BIT_ARST 0x80 /* AUTO RESET ENABLE BIT */
61#define RTC_STAT_BIT_XTOSCB 0x40 /* CRYSTAL OSCILLATOR ENABLE BIT */
62#define RTC_STAT_BIT_WRTC 0x10 /* WRITE RTC ENABLE BIT */
63#define RTC_STAT_BIT_ALM 0x04 /* ALARM BIT */
64#define RTC_STAT_BIT_BAT 0x02 /* BATTERY BIT */
65#define RTC_STAT_BIT_RTCF 0x01 /* REAL TIME CLOCK FAIL BIT */
66
67static uchar rtc_read (uchar reg);
68static void rtc_write (uchar reg, uchar val);
Tor Krill9536dfc2008-03-15 15:40:26 +010069
70/*
71 * Get the current time from the RTC
72 */
73
Yuri Tikhonovb73a19e2008-03-20 17:56:04 +030074int rtc_get (struct rtc_time *tmp)
Tor Krill9536dfc2008-03-15 15:40:26 +010075{
Yuri Tikhonovb73a19e2008-03-20 17:56:04 +030076 int rel = 0;
Tor Krill9536dfc2008-03-15 15:40:26 +010077 uchar sec, min, hour, mday, wday, mon, year, status;
78
79 status = rtc_read (RTC_STAT_REG_ADDR);
80 sec = rtc_read (RTC_SEC_REG_ADDR);
81 min = rtc_read (RTC_MIN_REG_ADDR);
82 hour = rtc_read (RTC_HR_REG_ADDR);
83 wday = rtc_read (RTC_DAY_REG_ADDR);
84 mday = rtc_read (RTC_DATE_REG_ADDR);
85 mon = rtc_read (RTC_MON_REG_ADDR);
86 year = rtc_read (RTC_YR_REG_ADDR);
87
88 DEBUGR ("Get RTC year: %02x mon: %02x mday: %02x wday: %02x "
89 "hr: %02x min: %02x sec: %02x status: %02x\n",
90 year, mon, mday, wday, hour, min, sec, status);
91
92 if (status & RTC_STAT_BIT_RTCF) {
93 printf ("### Warning: RTC oscillator has stopped\n");
94 rtc_write(RTC_STAT_REG_ADDR,
95 rtc_read(RTC_STAT_REG_ADDR) &~ (RTC_STAT_BIT_BAT|RTC_STAT_BIT_RTCF));
Yuri Tikhonovb73a19e2008-03-20 17:56:04 +030096 rel = -1;
Tor Krill9536dfc2008-03-15 15:40:26 +010097 }
98
99 tmp->tm_sec = bcd2bin (sec & 0x7F);
100 tmp->tm_min = bcd2bin (min & 0x7F);
101 tmp->tm_hour = bcd2bin (hour & 0x3F);
102 tmp->tm_mday = bcd2bin (mday & 0x3F);
103 tmp->tm_mon = bcd2bin (mon & 0x1F);
104 tmp->tm_year = bcd2bin (year)+2000;
105 tmp->tm_wday = bcd2bin (wday & 0x07);
106 tmp->tm_yday = 0;
107 tmp->tm_isdst= 0;
108
109 DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
110 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
111 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
Yuri Tikhonovb73a19e2008-03-20 17:56:04 +0300112
113 return rel;
Tor Krill9536dfc2008-03-15 15:40:26 +0100114}
115
116/*
117 * Set the RTC
118 */
Jean-Christophe PLAGNIOL-VILLARDd1e23192008-09-01 23:06:23 +0200119int rtc_set (struct rtc_time *tmp)
Tor Krill9536dfc2008-03-15 15:40:26 +0100120{
121 DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
122 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
123 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
124
125 /* enable write */
126 rtc_write(RTC_STAT_REG_ADDR,
127 rtc_read(RTC_STAT_REG_ADDR) | RTC_STAT_BIT_WRTC);
128
129 rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
130 rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon));
131 rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday));
132 rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
133 rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour) | 0x80 ); /* 24h clock */
134 rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
135 rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
136
137 /* disable write */
138 rtc_write(RTC_STAT_REG_ADDR,
139 rtc_read(RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_WRTC);
Jean-Christophe PLAGNIOL-VILLARDd1e23192008-09-01 23:06:23 +0200140
141 return 0;
Tor Krill9536dfc2008-03-15 15:40:26 +0100142}
143
144void rtc_reset (void)
145{
146}
147
148/*
149 * Helper functions
150 */
151
152static uchar rtc_read (uchar reg)
153{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154 return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
Tor Krill9536dfc2008-03-15 15:40:26 +0100155}
156
157static void rtc_write (uchar reg, uchar val)
158{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159 i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
Tor Krill9536dfc2008-03-15 15:40:26 +0100160}