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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +02002/*
3 * (C) Copyright 2009
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +02006 */
7
8#include <config.h>
Prafulla Wadaskarbeeb2582010-09-30 19:33:19 +05309#include <common.h>
Simon Glass9b4a2052019-12-28 10:45:05 -070010#include <init.h>
Simon Glass401d1c42020-10-30 21:38:53 -060011#include <asm/global_data.h>
Lei Wena7efd712011-10-18 20:11:42 +053012#include <asm/io.h>
13#include <asm/arch/cpu.h>
Stefan Roese3dc23f72014-10-22 12:13:06 +020014#include <asm/arch/soc.h>
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020015
Stefan Roese81e33f42015-12-21 13:56:33 +010016#if defined(CONFIG_ARCH_MVEBU)
17/* Use common XOR definitions for A3x and AXP */
Stefan Roese0ceb2da2015-08-06 14:43:13 +020018#include "../../../drivers/ddr/marvell/axp/xor.h"
19#include "../../../drivers/ddr/marvell/axp/xor_regs.h"
Stefan Roese8a83c652015-08-03 13:15:31 +020020#endif
21
Prafulla Wadaskarbeeb2582010-09-30 19:33:19 +053022DECLARE_GLOBAL_DATA_PTR;
23
Stefan Roese96c5f082014-10-22 12:13:13 +020024struct sdram_bank {
Holger Brunckcf37c5d2012-07-20 02:34:24 +000025 u32 win_bar;
26 u32 win_sz;
27};
28
Stefan Roese96c5f082014-10-22 12:13:13 +020029struct sdram_addr_dec {
30 struct sdram_bank sdram_bank[4];
Holger Brunckcf37c5d2012-07-20 02:34:24 +000031};
32
Stefan Roese96c5f082014-10-22 12:13:13 +020033#define REG_CPUCS_WIN_ENABLE (1 << 0)
34#define REG_CPUCS_WIN_WR_PROTECT (1 << 1)
35#define REG_CPUCS_WIN_WIN0_CS(x) (((x) & 0x3) << 2)
36#define REG_CPUCS_WIN_SIZE(x) (((x) & 0xff) << 24)
Gerlando Falauto45515162012-07-20 02:34:25 +000037
Stefan Roesea8483502018-10-22 14:21:17 +020038#ifndef MVEBU_SDRAM_SIZE_MAX
39#define MVEBU_SDRAM_SIZE_MAX 0xc0000000
40#endif
Stefan Roesea8b57a92015-08-10 15:11:27 +020041
Stefan Roese0ceb2da2015-08-06 14:43:13 +020042#define SCRUB_MAGIC 0xbeefdead
43
44#define SCRB_XOR_UNIT 0
45#define SCRB_XOR_CHAN 1
46#define SCRB_XOR_WIN 0
47
48#define XEBARX_BASE_OFFS 16
49
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020050/*
Stefan Roese96c5f082014-10-22 12:13:13 +020051 * mvebu_sdram_bar - reads SDRAM Base Address Register
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020052 */
Stefan Roese96c5f082014-10-22 12:13:13 +020053u32 mvebu_sdram_bar(enum memory_bank bank)
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020054{
Stefan Roese96c5f082014-10-22 12:13:13 +020055 struct sdram_addr_dec *base =
56 (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020057 u32 result = 0;
Holger Brunckcf37c5d2012-07-20 02:34:24 +000058 u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020059
60 if ((!enable) || (bank > BANK3))
61 return 0;
62
Holger Brunckcf37c5d2012-07-20 02:34:24 +000063 result = readl(&base->sdram_bank[bank].win_bar);
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020064 return result;
65}
66
67/*
Stefan Roese96c5f082014-10-22 12:13:13 +020068 * mvebu_sdram_bs_set - writes SDRAM Bank size
Gerlando Falauto45515162012-07-20 02:34:25 +000069 */
Stefan Roese96c5f082014-10-22 12:13:13 +020070static void mvebu_sdram_bs_set(enum memory_bank bank, u32 size)
Gerlando Falauto45515162012-07-20 02:34:25 +000071{
Stefan Roese96c5f082014-10-22 12:13:13 +020072 struct sdram_addr_dec *base =
73 (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
Gerlando Falauto45515162012-07-20 02:34:25 +000074 /* Read current register value */
75 u32 reg = readl(&base->sdram_bank[bank].win_sz);
76
77 /* Clear window size */
Stefan Roese96c5f082014-10-22 12:13:13 +020078 reg &= ~REG_CPUCS_WIN_SIZE(0xFF);
Gerlando Falauto45515162012-07-20 02:34:25 +000079
80 /* Set new window size */
Stefan Roese96c5f082014-10-22 12:13:13 +020081 reg |= REG_CPUCS_WIN_SIZE((size - 1) >> 24);
Gerlando Falauto45515162012-07-20 02:34:25 +000082
83 writel(reg, &base->sdram_bank[bank].win_sz);
84}
85
86/*
Stefan Roese96c5f082014-10-22 12:13:13 +020087 * mvebu_sdram_bs - reads SDRAM Bank size
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020088 */
Stefan Roese96c5f082014-10-22 12:13:13 +020089u32 mvebu_sdram_bs(enum memory_bank bank)
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020090{
Stefan Roese96c5f082014-10-22 12:13:13 +020091 struct sdram_addr_dec *base =
92 (struct sdram_addr_dec *)MVEBU_SDRAM_BASE;
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020093 u32 result = 0;
Holger Brunckcf37c5d2012-07-20 02:34:24 +000094 u32 enable = 0x01 & readl(&base->sdram_bank[bank].win_sz);
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020095
96 if ((!enable) || (bank > BANK3))
97 return 0;
Holger Brunckcf37c5d2012-07-20 02:34:24 +000098 result = 0xff000000 & readl(&base->sdram_bank[bank].win_sz);
Prafulla Wadaskar4efb77d2009-06-20 11:01:53 +020099 result += 0x01000000;
100 return result;
101}
Prafulla Wadaskarbeeb2582010-09-30 19:33:19 +0530102
Stefan Roese96c5f082014-10-22 12:13:13 +0200103void mvebu_sdram_size_adjust(enum memory_bank bank)
Gerlando Falautob3168f42012-07-25 06:23:48 +0000104{
105 u32 size;
106
107 /* probe currently equipped RAM size */
Stefan Roese96c5f082014-10-22 12:13:13 +0200108 size = get_ram_size((void *)mvebu_sdram_bar(bank),
109 mvebu_sdram_bs(bank));
Gerlando Falautob3168f42012-07-25 06:23:48 +0000110
111 /* adjust SDRAM window size accordingly */
Stefan Roese96c5f082014-10-22 12:13:13 +0200112 mvebu_sdram_bs_set(bank, size);
Gerlando Falautob3168f42012-07-25 06:23:48 +0000113}
114
Stefan Roese81e33f42015-12-21 13:56:33 +0100115#if defined(CONFIG_ARCH_MVEBU)
Stefan Roese0ceb2da2015-08-06 14:43:13 +0200116static u32 xor_ctrl_save;
117static u32 xor_base_save;
118static u32 xor_mask_save;
119
120static void mv_xor_init2(u32 cs)
121{
122 u32 reg, base, size, base2;
123 u32 bank_attr[4] = { 0xe00, 0xd00, 0xb00, 0x700 };
124
125 xor_ctrl_save = reg_read(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT,
126 SCRB_XOR_CHAN));
127 xor_base_save = reg_read(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT,
128 SCRB_XOR_WIN));
129 xor_mask_save = reg_read(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT,
130 SCRB_XOR_WIN));
131
132 /* Enable Window x for each CS */
133 reg = 0x1;
134 reg |= (0x3 << 16);
135 reg_write(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT, SCRB_XOR_CHAN), reg);
136
137 base = 0;
138 size = mvebu_sdram_bs(cs) - 1;
139 if (size) {
140 base2 = ((base / (64 << 10)) << XEBARX_BASE_OFFS) |
141 bank_attr[cs];
142 reg_write(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN),
143 base2);
144
145 base += size + 1;
146 size = (size / (64 << 10)) << 16;
147 /* Window x - size - 256 MB */
148 reg_write(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN), size);
149 }
150
151 mv_xor_hal_init(0);
152
153 return;
154}
155
156static void mv_xor_finish2(void)
157{
158 reg_write(XOR_WINDOW_CTRL_REG(SCRB_XOR_UNIT, SCRB_XOR_CHAN),
159 xor_ctrl_save);
160 reg_write(XOR_BASE_ADDR_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN),
161 xor_base_save);
162 reg_write(XOR_SIZE_MASK_REG(SCRB_XOR_UNIT, SCRB_XOR_WIN),
163 xor_mask_save);
164}
165
166static void dram_ecc_scrubbing(void)
167{
168 int cs;
169 u32 size, temp;
170 u32 total_mem = 0;
171 u64 total;
172 u32 start_addr;
173
174 /*
175 * The DDR training code from the bin_hdr / SPL already
176 * scrubbed the DDR till 0x1000000. And the main U-Boot
177 * is loaded to an address < 0x1000000. So we need to
178 * skip this range to not re-scrub this area again.
179 */
180 temp = reg_read(REG_SDRAM_CONFIG_ADDR);
181 temp |= (1 << REG_SDRAM_CONFIG_IERR_OFFS);
182 reg_write(REG_SDRAM_CONFIG_ADDR, temp);
183
184 for (cs = 0; cs < CONFIG_NR_DRAM_BANKS; cs++) {
Chris Packhamc3ab2742017-09-23 04:50:31 +1200185 size = mvebu_sdram_bs(cs);
Stefan Roese0ceb2da2015-08-06 14:43:13 +0200186 if (size == 0)
187 continue;
188
Chris Packhamc3ab2742017-09-23 04:50:31 +1200189 total = (u64)size;
Stefan Roese0ceb2da2015-08-06 14:43:13 +0200190 total_mem += (u32)(total / (1 << 30));
191 start_addr = 0;
192 mv_xor_init2(cs);
193
194 /* Skip first 16 MiB */
195 if (0 == cs) {
196 start_addr = 0x1000000;
197 size -= start_addr;
198 }
199
Chris Packhamc3ab2742017-09-23 04:50:31 +1200200 mv_xor_mem_init(SCRB_XOR_CHAN, start_addr, size - 1,
Stefan Roese0ceb2da2015-08-06 14:43:13 +0200201 SCRUB_MAGIC, SCRUB_MAGIC);
202
203 /* Wait for previous transfer completion */
204 while (mv_xor_state_get(SCRB_XOR_CHAN) != MV_IDLE)
205 ;
206
207 mv_xor_finish2();
208 }
209
210 temp = reg_read(REG_SDRAM_CONFIG_ADDR);
211 temp &= ~(1 << REG_SDRAM_CONFIG_IERR_OFFS);
212 reg_write(REG_SDRAM_CONFIG_ADDR, temp);
213}
214
215static int ecc_enabled(void)
216{
217 if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_ECC_OFFS))
218 return 1;
219
220 return 0;
221}
Joshua Scott631407c2017-09-04 17:38:32 +1200222
223/* Return the width of the DRAM bus, or 0 for unknown. */
224static int bus_width(void)
225{
226 int full_width = 0;
227
228 if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_WIDTH_OFFS))
229 full_width = 1;
230
231 switch (mvebu_soc_family()) {
232 case MVEBU_SOC_AXP:
233 return full_width ? 64 : 32;
234 break;
235 case MVEBU_SOC_A375:
236 case MVEBU_SOC_A38X:
237 case MVEBU_SOC_MSYS:
238 return full_width ? 32 : 16;
239 default:
240 return 0;
241 }
242}
243
244static int cycle_mode(void)
245{
246 int val = reg_read(REG_DUNIT_CTRL_LOW_ADDR);
247
248 return (val >> REG_DUNIT_CTRL_LOW_2T_OFFS) & REG_DUNIT_CTRL_LOW_2T_MASK;
249}
250
Stefan Roese0ceb2da2015-08-06 14:43:13 +0200251#else
252static void dram_ecc_scrubbing(void)
253{
254}
255
256static int ecc_enabled(void)
257{
258 return 0;
259}
260#endif
261
Prafulla Wadaskarbeeb2582010-09-30 19:33:19 +0530262int dram_init(void)
263{
Stefan Roesea8b57a92015-08-10 15:11:27 +0200264 u64 size = 0;
Prafulla Wadaskarbeeb2582010-09-30 19:33:19 +0530265 int i;
266
Prafulla Wadaskarbeeb2582010-09-30 19:33:19 +0530267 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
Prafulla Wadaskarbeeb2582010-09-30 19:33:19 +0530268 /*
269 * It is assumed that all memory banks are consecutive
270 * and without gaps.
271 * If the gap is found, ram_size will be reported for
272 * consecutive memory only
273 */
Stefan Roesea8b57a92015-08-10 15:11:27 +0200274 if (mvebu_sdram_bar(i) != size)
Prafulla Wadaskarbeeb2582010-09-30 19:33:19 +0530275 break;
276
Stefan Roesed80cca22014-10-22 12:13:05 +0200277 /*
278 * Don't report more than 3GiB of SDRAM, otherwise there is no
279 * address space left for the internal registers etc.
280 */
Stefan Roesea8b57a92015-08-10 15:11:27 +0200281 size += mvebu_sdram_bs(i);
Stefan Roesea8483502018-10-22 14:21:17 +0200282 if (size > MVEBU_SDRAM_SIZE_MAX)
283 size = MVEBU_SDRAM_SIZE_MAX;
Prafulla Wadaskarbeeb2582010-09-30 19:33:19 +0530284 }
Tanmay Upadhyay28e57102010-10-28 20:06:22 +0530285
Stefan Roese0ceb2da2015-08-06 14:43:13 +0200286 if (ecc_enabled())
287 dram_ecc_scrubbing();
288
Stefan Roesea8b57a92015-08-10 15:11:27 +0200289 gd->ram_size = size;
290
Prafulla Wadaskarbeeb2582010-09-30 19:33:19 +0530291 return 0;
292}
293
294/*
295 * If this function is not defined here,
296 * board.c alters dram bank zero configuration defined above.
297 */
Simon Glass76b00ac2017-03-31 08:40:32 -0600298int dram_init_banksize(void)
Prafulla Wadaskarbeeb2582010-09-30 19:33:19 +0530299{
Stefan Roesea8b57a92015-08-10 15:11:27 +0200300 u64 size = 0;
301 int i;
302
303 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
304 gd->bd->bi_dram[i].start = mvebu_sdram_bar(i);
305 gd->bd->bi_dram[i].size = mvebu_sdram_bs(i);
306
307 /* Clip the banksize to 1GiB if it exceeds the max size */
308 size += gd->bd->bi_dram[i].size;
Stefan Roesea8483502018-10-22 14:21:17 +0200309 if (size > MVEBU_SDRAM_SIZE_MAX)
Stefan Roesea8b57a92015-08-10 15:11:27 +0200310 mvebu_sdram_bs_set(i, 0x40000000);
311 }
Simon Glass76b00ac2017-03-31 08:40:32 -0600312
313 return 0;
Prafulla Wadaskarbeeb2582010-09-30 19:33:19 +0530314}
Stefan Roese8a83c652015-08-03 13:15:31 +0200315
Stefan Roese81e33f42015-12-21 13:56:33 +0100316#if defined(CONFIG_ARCH_MVEBU)
Stefan Roese8a83c652015-08-03 13:15:31 +0200317void board_add_ram_info(int use_default)
318{
Stefan Roesed718bf22015-12-21 12:36:40 +0100319 struct sar_freq_modes sar_freq;
Joshua Scott631407c2017-09-04 17:38:32 +1200320 int mode;
321 int width;
Stefan Roesed718bf22015-12-21 12:36:40 +0100322
323 get_sar_freq(&sar_freq);
324 printf(" (%d MHz, ", sar_freq.d_clk);
325
Joshua Scott631407c2017-09-04 17:38:32 +1200326 width = bus_width();
327 if (width)
328 printf("%d-bit, ", width);
329
330 mode = cycle_mode();
331 /* Mode 0 = Single cycle
332 * Mode 1 = Two cycles (2T)
333 * Mode 2 = Three cycles (3T)
334 */
335 if (mode == 1)
336 printf("2T, ");
337 if (mode == 2)
338 printf("3T, ");
339
Stefan Roese0ceb2da2015-08-06 14:43:13 +0200340 if (ecc_enabled())
Stefan Roesed718bf22015-12-21 12:36:40 +0100341 printf("ECC");
Stefan Roese8a83c652015-08-03 13:15:31 +0200342 else
Stefan Roesed718bf22015-12-21 12:36:40 +0100343 printf("ECC not");
Stefan Roese8a83c652015-08-03 13:15:31 +0200344 printf(" enabled)");
345}
Stefan Roesed718bf22015-12-21 12:36:40 +0100346#endif