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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Sergei Poselenov5d108ac2008-04-30 11:42:50 +02002/*
3 * (C) Copyright 2008
4 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
5 *
6 * Copyright 2004 Freescale Semiconductor.
7 * (C) Copyright 2002,2003, Motorola Inc.
8 * Xianghua Xiao, (X.Xiao@motorola.com)
9 *
10 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020011 */
12
13#include <common.h>
Simon Glassd96c2602019-12-28 10:44:58 -070014#include <clock_legacy.h>
Simon Glass3a7d5572019-08-01 09:46:42 -060015#include <env.h>
Simon Glass691d7192020-05-10 11:40:02 -060016#include <init.h>
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020017#include <pci.h>
Simon Glassb79fdc72020-05-10 11:39:54 -060018#include <uuid.h>
Simon Glass401d1c42020-10-30 21:38:53 -060019#include <asm/global_data.h>
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020020#include <asm/processor.h>
21#include <asm/immap_85xx.h>
22#include <ioports.h>
23#include <flash.h>
Simon Glassc05ed002020-05-10 11:40:11 -060024#include <linux/delay.h>
Masahiro Yamadab08c8c42018-03-05 01:20:11 +090025#include <linux/libfdt.h>
Sergei Poselenove18575d2008-05-07 15:10:49 +020026#include <fdt_support.h>
Andy Fleminge1eb0e22008-06-10 18:49:34 -050027#include <asm/io.h>
u-boot@bugs.denx.defb661ea2008-09-11 15:40:01 +020028#include <i2c.h>
29#include <mb862xx.h>
30#include <video_fb.h>
Sergei Poselenov59abd152008-06-06 15:42:41 +020031#include "upm_table.h"
Detlev Zundel3e79b582008-08-15 15:42:12 +020032
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020033DECLARE_GLOBAL_DATA_PTR;
34
35extern flash_info_t flash_info[]; /* FLASH chips info */
u-boot@bugs.denx.defb661ea2008-09-11 15:40:01 +020036extern GraphicDevice mb862xx;
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020037
38void local_bus_init (void);
39ulong flash_get_size (ulong base, int banknum);
40
41int checkboard (void)
42{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020043 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +000044 char buf[64];
Sergei Poselenov5e1882d2008-05-27 13:47:00 +020045 int f;
Simon Glass00caae62017-08-03 12:22:12 -060046 int i = env_get_f("serial#", buf, sizeof(buf));
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +000047#ifdef CONFIG_PCI
48 char *src;
49#endif
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020050
51 puts("Board: Socrates");
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +000052 if (i > 0) {
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020053 puts(", serial# ");
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +000054 puts(buf);
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020055 }
56 putc('\n');
57
Heiko Schocher2a51fe02019-10-16 05:55:54 +020058#if defined(CONFIG_PCI) || defined(CONFIG_DM_PCI)
Andy Fleminge1eb0e22008-06-10 18:49:34 -050059 /* Check the PCI_clk sel bit */
60 if (in_be32(&gur->porpllsr) & (1<<15)) {
Sergei Poselenov5e1882d2008-05-27 13:47:00 +020061 src = "SYSCLK";
62 f = CONFIG_SYS_CLK_FREQ;
63 } else {
64 src = "PCI_CLK";
65 f = CONFIG_PCI_CLK_FREQ;
66 }
67 printf ("PCI1: 32 bit, %d MHz (%s)\n", f/1000000, src);
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020068#else
69 printf ("PCI1: disabled\n");
70#endif
71
72 /*
73 * Initialize local bus.
74 */
75 local_bus_init ();
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020076 return 0;
77}
78
79int misc_init_r (void)
80{
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020081 /*
82 * Adjust flash start and offset to detected values
83 */
84 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
85 gd->bd->bi_flashoffset = 0;
86
87 /*
88 * Check if boot FLASH isn't max size
89 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090 if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) {
Becky Brucef51cdaf2010-06-17 11:37:20 -050091 set_lbc_or(0, gd->bd->bi_flashstart |
92 (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
93 set_lbc_br(0, gd->bd->bi_flashstart |
94 (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
Sergei Poselenov5d108ac2008-04-30 11:42:50 +020095
96 /*
97 * Re-check to get correct base address
98 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099 flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200100 }
101
102 /*
103 * Check if only one FLASH bank is available
104 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105 if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
Becky Brucef51cdaf2010-06-17 11:37:20 -0500106 set_lbc_or(1, 0);
107 set_lbc_br(1, 0);
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200108
109 /*
110 * Re-do flash protection upon new addresses
111 */
Simon Glassa595a0e2020-05-10 11:39:53 -0600112 flash_protect(FLAG_PROTECT_CLEAR,
113 gd->bd->bi_flashstart, 0xffffffff,
114 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200115
116 /* Monitor protection ON by default */
Simon Glassa595a0e2020-05-10 11:39:53 -0600117 flash_protect(FLAG_PROTECT_SET,
118 CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE +
119 monitor_flash_len - 1,
120 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200121
122 /* Environment protection ON by default */
Simon Glassa595a0e2020-05-10 11:39:53 -0600123 flash_protect(FLAG_PROTECT_SET,
124 CONFIG_ENV_ADDR,
125 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
126 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200127
128 /* Redundant environment protection ON by default */
Simon Glassa595a0e2020-05-10 11:39:53 -0600129 flash_protect(FLAG_PROTECT_SET,
130 CONFIG_ENV_ADDR_REDUND,
131 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132 &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200133 }
134
Heiko Schocher2a51fe02019-10-16 05:55:54 +0200135#if defined(CONFIG_DM_PCI)
136 pci_init();
137#endif
138
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200139 return 0;
140}
141
142/*
143 * Initialize Local Bus
144 */
145void local_bus_init (void)
146{
Becky Brucef51cdaf2010-06-17 11:37:20 -0500147 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
Detlev Zundel3e79b582008-08-15 15:42:12 +0200149 sys_info_t sysinfo;
150 uint clkdiv;
151 uint lbc_mhz;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152 uint lcrr = CONFIG_SYS_LBC_LCRR;
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200153
Detlev Zundel3e79b582008-08-15 15:42:12 +0200154 get_sys_info (&sysinfo);
Trent Piephoa5d212a2008-12-03 15:16:34 -0800155 clkdiv = lbc->lcrr & LCRR_CLKDIV;
Prabhakar Kushwaha997399f2013-08-16 14:52:26 +0530156 lbc_mhz = sysinfo.freq_systembus / 1000000 / clkdiv;
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200157
Detlev Zundel3e79b582008-08-15 15:42:12 +0200158 /* Disable PLL bypass for Local Bus Clock >= 66 MHz */
159 if (lbc_mhz >= 66)
160 lcrr &= ~LCRR_DBYP; /* DLL Enabled */
161 else
162 lcrr |= LCRR_DBYP; /* DLL Bypass */
163
164 out_be32 (&lbc->lcrr, lcrr);
165 asm ("sync;isync;msync");
166
167 out_be32 (&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */
168 out_be32 (&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */
169 out_be32 (&ecm->eedr, 0xffffffff); /* Clear ecm errors */
170 out_be32 (&ecm->eeer, 0xffffffff); /* Enable ecm errors */
171
172 /* Init UPMA for FPGA access */
173 out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */
Simon Glass6d1fdb12019-12-28 10:44:57 -0700174 upmconfig(UPMA, (uint *)UPMTableA, sizeof(UPMTableA) / sizeof(int));
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200175
u-boot@bugs.denx.defb661ea2008-09-11 15:40:01 +0200176 /* Init UPMB for Lime controller access */
177 out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */
Simon Glass6d1fdb12019-12-28 10:44:57 -0700178 upmconfig(UPMB, (uint *)UPMTableB, sizeof(UPMTableB) / sizeof(int));
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200179}
180
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200181#ifdef CONFIG_BOARD_EARLY_INIT_R
182int board_early_init_r (void)
183{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Detlev Zundel3e79b582008-08-15 15:42:12 +0200185
186 /* set and reset the GPIO pin 2 which will reset the W83782G chip */
187 out_8((unsigned char*)&gur->gpoutdr, 0x3F );
188 out_be32((unsigned int*)&gur->gpiocr, 0x200 ); /* enable GPOut */
189 udelay(200);
190 out_8( (unsigned char*)&gur->gpoutdr, 0x1F );
191
Sergei Poselenov5d108ac2008-04-30 11:42:50 +0200192 return (0);
193}
194#endif /* CONFIG_BOARD_EARLY_INIT_R */
Sergei Poselenove18575d2008-05-07 15:10:49 +0200195
Robert P. J. Day7ffe3cd2016-05-19 15:23:12 -0400196#ifdef CONFIG_OF_BOARD_SETUP
Masahiro Yamadab75d8dc2020-06-26 15:13:33 +0900197int ft_board_setup(void *blob, struct bd_info *bd)
Sergei Poselenove18575d2008-05-07 15:10:49 +0200198{
Detlev Zundel3e79b582008-08-15 15:42:12 +0200199 u32 val[12];
200 int rc, i = 0;
Sergei Poselenove18575d2008-05-07 15:10:49 +0200201
202 ft_cpu_setup(blob, bd);
203
Detlev Zundel3e79b582008-08-15 15:42:12 +0200204 /* Fixup NOR FLASH mapping */
205 val[i++] = 0; /* chip select number */
206 val[i++] = 0; /* always 0 */
207 val[i++] = gd->bd->bi_flashstart;
208 val[i++] = gd->bd->bi_flashsize;
209
Heiko Schocher4c65a442019-10-16 05:55:51 +0200210#if defined(CONFIG_VIDEO_MB862xx)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211 if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) {
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200212 /* Fixup LIME mapping */
213 val[i++] = 2; /* chip select number */
214 val[i++] = 0; /* always 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215 val[i++] = CONFIG_SYS_LIME_BASE;
216 val[i++] = CONFIG_SYS_LIME_SIZE;
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200217 }
Heiko Schocher4c65a442019-10-16 05:55:51 +0200218#endif
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200219
Detlev Zundel3e79b582008-08-15 15:42:12 +0200220 /* Fixup FPGA mapping */
221 val[i++] = 3; /* chip select number */
222 val[i++] = 0; /* always 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223 val[i++] = CONFIG_SYS_FPGA_BASE;
224 val[i++] = CONFIG_SYS_FPGA_SIZE;
Sergei Poselenove18575d2008-05-07 15:10:49 +0200225
226 rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
Detlev Zundel3e79b582008-08-15 15:42:12 +0200227 val, i * sizeof(u32), 1);
Sergei Poselenove18575d2008-05-07 15:10:49 +0200228 if (rc)
Detlev Zundel3e79b582008-08-15 15:42:12 +0200229 printf("Unable to update localbus ranges, err=%s\n",
Sergei Poselenove18575d2008-05-07 15:10:49 +0200230 fdt_strerror(rc));
Simon Glasse895a4b2014-10-23 18:58:47 -0600231
232 return 0;
Sergei Poselenove18575d2008-05-07 15:10:49 +0200233}
Robert P. J. Day7ffe3cd2016-05-19 15:23:12 -0400234#endif /* CONFIG_OF_BOARD_SETUP */
Anatolij Gustschine64987a2008-08-15 15:42:13 +0200235
Heiko Schocher39642ab2019-10-16 05:55:49 +0200236#if defined(CONFIG_OF_SEPARATE)
237void *board_fdt_blob_setup(void)
238{
239 void *fw_dtb;
240
241 fw_dtb = (void *)(CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SECT_SIZE);
242 if (fdt_magic(fw_dtb) != FDT_MAGIC) {
243 printf("DTB is not passed via %x\n", (u32)fw_dtb);
244 return NULL;
245 }
246
247 return fw_dtb;
248}
249#endif
Heiko Schocher98beb602019-10-16 05:55:53 +0200250
251int get_serial_clock(void)
252{
253 return 333333330;
254}